Generate block labels in the ARM hybrid assembler.

Generate block labels in the ARM hybrid assembler.

Fixes an issue where branches don't compile in the hybrid integrated
assembler because some jump instructions have not yet been integrated.
It does this by adding an instruction label for each corresponding
label generated by the standalone ARM assembler.

Note that in order to fix this, I had to change the signature of
virtual method Assembler::bindCfgNodeLabel to get the Cfg node (rather
than the index value). This allows the ARM hybrid assembler to
generate a label for each CfgNode (using the getAsmName() method).

BUG= https://code.google.com/p/nativeclient/issues/detail?id=4334
R=stichnot@chromium.org

Committed: https://gerrit.chromium.org/gerrit/gitweb?p=native_client/pnacl-subzero.git;a=commit;h=50a3331c517ea0945987b616f4c5cf607aa81b9b

[Karl, 2015-10-22 20:05:20]

Description was changed from

==========
Generate block labels in ARM integrated assembler.

Fixes an issue where branches don't compile in the hybrid integrated
assembler because some jump instructions have not yet been integrated.
It does this by adding an instruction label for each corresponding
label generated by the standalone ARM assembler.

Note that in order to fix this, I had to change the signature of
virtual method Assembler::bindCfgNodeLabel to get the Cfg node (rather
than the index value). This allows the ARM hybrid assembler to
generate a label for ech CfgNode (using the getAsmName() method).

BUG= https://code.google.com/p/nativeclient/issues/detail?id=4334
==========

to

==========
Generate block labels in the ARM hybrid assembler.

Fixes an issue where branches don't compile in the hybrid integrated
assembler because some jump instructions have not yet been integrated.
It does this by adding an instruction label for each corresponding
label generated by the standalone ARM assembler.

Note that in order to fix this, I had to change the signature of
virtual method Assembler::bindCfgNodeLabel to get the Cfg node (rather
than the index value). This allows the ARM hybrid assembler to
generate a label for each CfgNode (using the getAsmName() method).

BUG= https://code.google.com/p/nativeclient/issues/detail?id=4334
==========

[Karl, 2015-10-22 20:15:05]

kschimpf@google.com changed reviewers:
+ jpp@chromium.org, sehr@google.com, stichnot@chromium.org

[Jim Stichnoth, 2015-10-23 13:54:52]

lgtm

https://codereview.chromium.org/1407273006/diff/20001/src/IceAssemblerARM32.cpp
File src/IceAssemblerARM32.cpp (right):

https://codereview.chromium.org/1407273006/diff/20001/src/IceAssemblerARM32.c...
src/IceAssemblerARM32.cpp:211: emitTextInst(Node->getAsmName() + ":", 0);
Can you use "constexpr SizeT InstSize = 0;" for the "0" arg?

[Karl, 2015-10-23 16:19:53]

Committed patchset #3 (id:40001) manually as
50a3331c517ea0945987b616f4c5cf607aa81b9b (presubmit successful).

[Karl, 2015-10-23 16:20:07]

https://chromiumcodereview.appspot.com/1407273006/diff/20001/src/IceAssembler...
File src/IceAssemblerARM32.cpp (right):

https://chromiumcodereview.appspot.com/1407273006/diff/20001/src/IceAssembler...
src/IceAssemblerARM32.cpp:211: emitTextInst(Node->getAsmName() + ":", 0);
On 2015/10/23 13:54:52, stichnot wrote:
> Can you use "constexpr SizeT InstSize = 0;" for the "0" arg?

Done.