Generate block labels in the ARM hybrid assembler.

src/IceAssemblerARM32.cpp

 //===- subzero/src/IceAssemblerARM32.cpp - Assembler for ARM32 --*- C++ -*-===//
 //
 // Copyright (c) 2013, the Dart project authors.  Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE file.
 //
 // Modified by the Subzero authors.
 //
 //===----------------------------------------------------------------------===//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 ///
 /// \file
 /// This file implements the Assembler class for ARM32.
 ///
 //===----------------------------------------------------------------------===//
 
 #include "IceAssemblerARM32.h"
+#include "IceCfgNode.h"
 #include "IceUtils.h"
 
 namespace {
 
 using namespace Ice;
 
 // The following define individual bits.
 static constexpr uint32_t B0 = 1;
 static constexpr uint32_t B1 = 1 << 1;
 static constexpr uint32_t B2 = 1 << 2;
@@ skipping 163 matching lines @@
                                OperandARM32Mem::Offset);
     return DecodedAsImmRegOffset;
   }
   return CantDecode;
 }
 
 } // end of anonymous namespace
 
 namespace Ice {
 
+void ARM32::AssemblerARM32::bindCfgNodeLabel(const CfgNode *Node) {
+  if (BuildDefs::dump() && !Ctx->getFlags().getDisableHybridAssembly()) {
+    // Generate label name so that branches can find it.
+    emitTextInst(Node->getAsmName() + ":", 0);

[Jim Stichnoth, 2015/10/23 13:54:52]

Can you use "constexpr SizeT InstSize = 0;" for the "0" arg?

[Karl, 2015/10/23 16:20:07]

Done.

+  }
+  SizeT NodeNumber = Node->getIndex();
+  assert(!getPreliminary());
+  Label *L = getOrCreateCfgNodeLabel(NodeNumber);
+  this->bind(L);
+}
+
 Label *ARM32::AssemblerARM32::getOrCreateLabel(SizeT Number,
                                                LabelVector &Labels) {
   Label *L = nullptr;
   if (Number == Labels.size()) {
     L = new (this->allocate<Label>()) Label();
     Labels.push_back(L);
     return L;
   }
   if (Number > Labels.size()) {
     Labels.resize(Number + 1);
@@ skipping 12 matching lines @@
   while (label->isLinked()) {
     intptr_t position = label->getLinkPosition();
     intptr_t next = Buffer.load<int32_t>(position);
     Buffer.store<int32_t>(position, bound - (position + 4));
     label->setPosition(next);
   }
   // TODO(kschimpf) Decide if we have near jumps.
   label->bindTo(bound);
 }
 
-void ARM32::AssemblerARM32::emitTextInst(const std::string &Text) {
-  static constexpr uint32_t Placeholder = 0;
+void ARM32::AssemblerARM32::emitTextInst(const std::string &Text,
+                                         SizeT InstSize) {
   AssemblerBuffer::EnsureCapacity ensured(&Buffer);
-  AssemblerFixup *F = createTextFixup(Text, sizeof(Placeholder));
+  AssemblerFixup *F = createTextFixup(Text, InstSize);
   emitFixup(F);
-  emitInst(Placeholder);
+  for (SizeT I = 0; I < InstSize; ++I)
+    Buffer.emit<char>(0);
 }
 
 void ARM32::AssemblerARM32::emitType01(CondARM32::Cond Cond, uint32_t Type,
                                        uint32_t Opcode, bool SetCc, uint32_t Rn,
                                        uint32_t Rd, uint32_t Imm12) {
   assert(isGPRRegisterDefined(Rd));
   // TODO(kschimpf): Remove void cast when MINIMAL build allows.
   (void)isGPRRegisterDefined(Rd);
   assert(Cond != CondARM32::kNone);
   AssemblerBuffer::EnsureCapacity ensured(&Buffer);
@@ skipping 225 matching lines @@
     if (Rd == RegARM32::Encoded_Reg_pc)
       // Conditions of rule violated.
       return setNeedsTextFixup();
     emitType01(Cond, kInstTypeDataImmediate, Sub, SetFlags, Rn, Rd, Src1Value);
     return;
   }
   }
 }
 
 } // end of namespace Ice