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Issue 1407273006: Generate block labels in the ARM hybrid assembler. (Closed) Base URL: https://chromium.googlesource.com/native_client/pnacl-subzero.git@master
Patch Set: Fix nit. Created 5 years, 1 month ago
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1 ; Show that we know how to translate add. 1 ; Show that we know how to translate add.
2 2
3 ; NOTE: We use -O2 to get rid of memory stores. 3 ; NOTE: We use -O2 to get rid of memory stores.
4 4
5 ; REQUIRES: allow_dump 5 ; REQUIRES: allow_dump
6 6
7 ; Compile using standalone assembler. 7 ; Compile using standalone assembler.
8 ; RUN: %p2i --filetype=asm -i %s --target=arm32 --args -O2 \ 8 ; RUN: %p2i --filetype=asm -i %s --target=arm32 --args -O2 \
9 ; RUN: | FileCheck %s --check-prefix=ASM 9 ; RUN: | FileCheck %s --check-prefix=ASM
10 10
11 ; Show bytes in assembled standalone code. 11 ; Show bytes in assembled standalone code.
12 ; RUN: %p2i --filetype=asm -i %s --target=arm32 --assemble --disassemble \ 12 ; RUN: %p2i --filetype=asm -i %s --target=arm32 --assemble --disassemble \
13 ; RUN: --args -O2 | FileCheck %s --check-prefix=DIS 13 ; RUN: --args -O2 | FileCheck %s --check-prefix=DIS
14 14
15 ; Compile using integrated assembler. 15 ; Compile using integrated assembler.
16 ; RUN: %p2i --filetype=iasm -i %s --target=arm32 --args -O2 \ 16 ; RUN: %p2i --filetype=iasm -i %s --target=arm32 --args -O2 \
17 ; RUN: | FileCheck %s --check-prefix=IASM 17 ; RUN: | FileCheck %s --check-prefix=IASM
18 18
19 ; Show bytes in assembled integrated code. 19 ; Show bytes in assembled integrated code.
20 ; RUN: %p2i --filetype=iasm -i %s --target=arm32 --assemble --disassemble \ 20 ; RUN: %p2i --filetype=iasm -i %s --target=arm32 --assemble --disassemble \
21 ; RUN: --args -O2 | FileCheck %s --check-prefix=DIS 21 ; RUN: --args -O2 | FileCheck %s --check-prefix=DIS
22 22
23 define internal i32 @add1ToR0(i32 %p) { 23 define internal i32 @add1ToR0(i32 %p) {
24 %v = add i32 %p, 1 24 %v = add i32 %p, 1
25 ret i32 %v 25 ret i32 %v
26 } 26 }
27 27
28 ; ASM-LABEL: add1ToR0: 28 ; ASM-LABEL: add1ToR0:
29 ; ASM: add r0, r0, #1 29 ; ASM-NEXT: .Ladd1ToR0$__0:
30 ; ASM-NEXT: bx lr 30 ; ASM-NEXT: add r0, r0, #1
31 ; ASM-NEXT: bx lr
31 32
32 ; DIS-LABEL:00000000 <add1ToR0>: 33 ; DIS-LABEL:00000000 <add1ToR0>:
33 ; DIS-NEXT: 0: e2800001 34 ; DIS-NEXT: 0: e2800001
34 ; DIS-NEXT: 4: e12fff1e 35 ; DIS-NEXT: 4: e12fff1e
35 36
36 ; IASM-LABEL: add1ToR0: 37 ; IASM-LABEL: add1ToR0:
37 38 ; IASM-LABEL: .Ladd1ToR0$__0:
38 ; IASM-NEXT: .byte 0x1 39 ; IASM-NEXT: .byte 0x1
39 ; IASM-NEXT: .byte 0x0 40 ; IASM-NEXT: .byte 0x0
40 ; IASM-NEXT: .byte 0x80 41 ; IASM-NEXT: .byte 0x80
41 ; IASM-NEXT: .byte 0xe2 42 ; IASM-NEXT: .byte 0xe2
42 43
43 ; IASM-NEXT: .byte 0x1e 44 ; IASM-NEXT: .byte 0x1e
44 ; IASM-NEXT: .byte 0xff 45 ; IASM-NEXT: .byte 0xff
45 ; IASM-NEXT: .byte 0x2f 46 ; IASM-NEXT: .byte 0x2f
46 ; IASM-NEXT: .byte 0xe1 47 ; IASM-NEXT: .byte 0xe1
47 48
48 define internal i32 @Add2Regs(i32 %p1, i32 %p2) { 49 define internal i32 @Add2Regs(i32 %p1, i32 %p2) {
49 %v = add i32 %p1, %p2 50 %v = add i32 %p1, %p2
50 ret i32 %v 51 ret i32 %v
51 } 52 }
52 53
53 ; ASM-LABEL: Add2Regs: 54 ; ASM-LABEL: Add2Regs:
54 ; ASM: add r0, r0, r1 55 ; ASM-NEXT: .LAdd2Regs$__0:
55 ; ASM-NEXT: bx lr 56 ; ASM-NEXT: add r0, r0, r1
57 ; ASM-NEXT: bx lr
56 58
57 ; DIS-LABEL:00000010 <Add2Regs>: 59 ; DIS-LABEL:00000010 <Add2Regs>:
58 ; DIS-NEXT: 10: e0800001 60 ; DIS-NEXT: 10: e0800001
59 ; DIS-NEXT: 14: e12fff1e 61 ; DIS-NEXT: 14: e12fff1e
60 62
61 ; IASM-LABEL: Add2Regs: 63 ; IASM-LABEL: Add2Regs:
62 64 ; IASM-NEXT: .LAdd2Regs$__0:
63 ; IASM-NEXT: .byte 0x1 65 ; IASM-NEXT: .byte 0x1
64 ; IASM-NEXT: .byte 0x0 66 ; IASM-NEXT: .byte 0x0
65 ; IASM-NEXT: .byte 0x80 67 ; IASM-NEXT: .byte 0x80
66 ; IASM-NEXT: .byte 0xe0 68 ; IASM-NEXT: .byte 0xe0
67 69
68 ; IASM-NEXT: .byte 0x1e 70 ; IASM-NEXT: .byte 0x1e
69 ; IASM-NEXT: .byte 0xff 71 ; IASM-NEXT: .byte 0xff
70 ; IASM-NEXT: .byte 0x2f 72 ; IASM-NEXT: .byte 0x2f
71 ; IASM-NEXT: .byte 0xe1 73 ; IASM-NEXT: .byte 0xe1
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