Revert r12646 "Support for SDIV" because of failing V8 benchmark.

src/arm/disasm-arm.cc

Index: src/arm/disasm-arm.cc
diff --git a/src/arm/disasm-arm.cc b/src/arm/disasm-arm.cc
index 7c5f63edc903426db7af7f87adcaf06a2ade1aa7..96a7d3ce6b6dfbc1d4c8bdf64e5ee53c9ba709ad 100644
--- a/src/arm/disasm-arm.cc
+++ b/src/arm/disasm-arm.cc
@@ -692,19 +692,11 @@ void Decoder::DecodeType01(Instruction* instr) {
             // Rn field to encode it.
             Format(instr, "mul'cond's 'rn, 'rm, 'rs");
           } else {
-            if (instr->Bit(22) == 0) {
-              // The MLA instruction description (A 4.1.28) refers to the order
-              // of registers as "Rd, Rm, Rs, Rn". But confusingly it uses the
-              // Rn field to encode the Rd register and the Rd field to encode
-              // the Rn register.
-              Format(instr, "mla'cond's 'rn, 'rm, 'rs, 'rd");
-            } else {
-              // The MLS instruction description (A 4.1.29) refers to the order
-              // of registers as "Rd, Rm, Rs, Rn". But confusingly it uses the
-              // Rn field to encode the Rd register and the Rd field to encode
-              // the Rn register.
-              Format(instr, "mls'cond's 'rn, 'rm, 'rs, 'rd");
-            }
+            // The MLA instruction description (A 4.1.28) refers to the order
+            // of registers as "Rd, Rm, Rs, Rn". But confusingly it uses the
+            // Rn field to encode the Rd register and the Rd field to encode
+            // the Rn register.
+            Format(instr, "mla'cond's 'rn, 'rm, 'rs, 'rd");
           }
         } else {
           // The signed/long multiply instructions use the terms RdHi and RdLo
@@ -982,17 +974,6 @@ void Decoder::DecodeType3(Instruction* instr) {
       break;
     }
     case db_x: {
-      if (FLAG_enable_sudiv) {
-        if (!instr->HasW()) {
-          if (instr->Bits(5, 4) == 0x1) {
-            if ((instr->Bit(22) == 0x0) && (instr->Bit(20) == 0x1)) {
-              // SDIV (in V8 notation matching ARM ISA format) rn = rm/rs
-              Format(instr, "sdiv'cond'b 'rn, 'rm, 'rs");
-              break;
-            }
-          }
-        }
-      }
       Format(instr, "'memop'cond'b 'rd, ['rn, -'shift_rm]'w");
       break;
     }