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1 // Copyright 2011 the V8 project authors. All rights reserved. | 1 // Copyright 2011 the V8 project authors. All rights reserved. |
2 // Redistribution and use in source and binary forms, with or without | 2 // Redistribution and use in source and binary forms, with or without |
3 // modification, are permitted provided that the following conditions are | 3 // modification, are permitted provided that the following conditions are |
4 // met: | 4 // met: |
5 // | 5 // |
6 // * Redistributions of source code must retain the above copyright | 6 // * Redistributions of source code must retain the above copyright |
7 // notice, this list of conditions and the following disclaimer. | 7 // notice, this list of conditions and the following disclaimer. |
8 // * Redistributions in binary form must reproduce the above | 8 // * Redistributions in binary form must reproduce the above |
9 // copyright notice, this list of conditions and the following | 9 // copyright notice, this list of conditions and the following |
10 // disclaimer in the documentation and/or other materials provided | 10 // disclaimer in the documentation and/or other materials provided |
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685 if (instr->Bits(7, 4) == 9) { | 685 if (instr->Bits(7, 4) == 9) { |
686 if (instr->Bit(24) == 0) { | 686 if (instr->Bit(24) == 0) { |
687 // multiply instructions | 687 // multiply instructions |
688 if (instr->Bit(23) == 0) { | 688 if (instr->Bit(23) == 0) { |
689 if (instr->Bit(21) == 0) { | 689 if (instr->Bit(21) == 0) { |
690 // The MUL instruction description (A 4.1.33) refers to Rd as being | 690 // The MUL instruction description (A 4.1.33) refers to Rd as being |
691 // the destination for the operation, but it confusingly uses the | 691 // the destination for the operation, but it confusingly uses the |
692 // Rn field to encode it. | 692 // Rn field to encode it. |
693 Format(instr, "mul'cond's 'rn, 'rm, 'rs"); | 693 Format(instr, "mul'cond's 'rn, 'rm, 'rs"); |
694 } else { | 694 } else { |
695 if (instr->Bit(22) == 0) { | 695 // The MLA instruction description (A 4.1.28) refers to the order |
696 // The MLA instruction description (A 4.1.28) refers to the order | 696 // of registers as "Rd, Rm, Rs, Rn". But confusingly it uses the |
697 // of registers as "Rd, Rm, Rs, Rn". But confusingly it uses the | 697 // Rn field to encode the Rd register and the Rd field to encode |
698 // Rn field to encode the Rd register and the Rd field to encode | 698 // the Rn register. |
699 // the Rn register. | 699 Format(instr, "mla'cond's 'rn, 'rm, 'rs, 'rd"); |
700 Format(instr, "mla'cond's 'rn, 'rm, 'rs, 'rd"); | |
701 } else { | |
702 // The MLS instruction description (A 4.1.29) refers to the order | |
703 // of registers as "Rd, Rm, Rs, Rn". But confusingly it uses the | |
704 // Rn field to encode the Rd register and the Rd field to encode | |
705 // the Rn register. | |
706 Format(instr, "mls'cond's 'rn, 'rm, 'rs, 'rd"); | |
707 } | |
708 } | 700 } |
709 } else { | 701 } else { |
710 // The signed/long multiply instructions use the terms RdHi and RdLo | 702 // The signed/long multiply instructions use the terms RdHi and RdLo |
711 // when referring to the target registers. They are mapped to the Rn | 703 // when referring to the target registers. They are mapped to the Rn |
712 // and Rd fields as follows: | 704 // and Rd fields as follows: |
713 // RdLo == Rd field | 705 // RdLo == Rd field |
714 // RdHi == Rn field | 706 // RdHi == Rn field |
715 // The order of registers is: <RdLo>, <RdHi>, <Rm>, <Rs> | 707 // The order of registers is: <RdLo>, <RdHi>, <Rm>, <Rs> |
716 Format(instr, "'um'al'cond's 'rd, 'rn, 'rm, 'rs"); | 708 Format(instr, "'um'al'cond's 'rd, 'rn, 'rm, 'rs"); |
717 } | 709 } |
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975 Format(instr, "usat 'rd, #'imm05@16, 'rm'shift_sat"); | 967 Format(instr, "usat 'rd, #'imm05@16, 'rm'shift_sat"); |
976 } else { | 968 } else { |
977 UNREACHABLE(); // SSAT. | 969 UNREACHABLE(); // SSAT. |
978 } | 970 } |
979 } else { | 971 } else { |
980 Format(instr, "'memop'cond'b 'rd, ['rn], +'shift_rm"); | 972 Format(instr, "'memop'cond'b 'rd, ['rn], +'shift_rm"); |
981 } | 973 } |
982 break; | 974 break; |
983 } | 975 } |
984 case db_x: { | 976 case db_x: { |
985 if (FLAG_enable_sudiv) { | |
986 if (!instr->HasW()) { | |
987 if (instr->Bits(5, 4) == 0x1) { | |
988 if ((instr->Bit(22) == 0x0) && (instr->Bit(20) == 0x1)) { | |
989 // SDIV (in V8 notation matching ARM ISA format) rn = rm/rs | |
990 Format(instr, "sdiv'cond'b 'rn, 'rm, 'rs"); | |
991 break; | |
992 } | |
993 } | |
994 } | |
995 } | |
996 Format(instr, "'memop'cond'b 'rd, ['rn, -'shift_rm]'w"); | 977 Format(instr, "'memop'cond'b 'rd, ['rn, -'shift_rm]'w"); |
997 break; | 978 break; |
998 } | 979 } |
999 case ib_x: { | 980 case ib_x: { |
1000 if (instr->HasW() && (instr->Bits(6, 4) == 0x5)) { | 981 if (instr->HasW() && (instr->Bits(6, 4) == 0x5)) { |
1001 uint32_t widthminus1 = static_cast<uint32_t>(instr->Bits(20, 16)); | 982 uint32_t widthminus1 = static_cast<uint32_t>(instr->Bits(20, 16)); |
1002 uint32_t lsbit = static_cast<uint32_t>(instr->Bits(11, 7)); | 983 uint32_t lsbit = static_cast<uint32_t>(instr->Bits(11, 7)); |
1003 uint32_t msbit = widthminus1 + lsbit; | 984 uint32_t msbit = widthminus1 + lsbit; |
1004 if (msbit <= 31) { | 985 if (msbit <= 31) { |
1005 if (instr->Bit(22)) { | 986 if (instr->Bit(22)) { |
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1526 pc += d.InstructionDecode(buffer, pc); | 1507 pc += d.InstructionDecode(buffer, pc); |
1527 fprintf(f, "%p %08x %s\n", | 1508 fprintf(f, "%p %08x %s\n", |
1528 prev_pc, *reinterpret_cast<int32_t*>(prev_pc), buffer.start()); | 1509 prev_pc, *reinterpret_cast<int32_t*>(prev_pc), buffer.start()); |
1529 } | 1510 } |
1530 } | 1511 } |
1531 | 1512 |
1532 | 1513 |
1533 } // namespace disasm | 1514 } // namespace disasm |
1534 | 1515 |
1535 #endif // V8_TARGET_ARCH_ARM | 1516 #endif // V8_TARGET_ARCH_ARM |
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