| Index: src/trusted/validator_arm/gen/arm32_decode_tests.cc
|
| diff --git a/src/trusted/validator_arm/gen/arm32_decode_tests.cc b/src/trusted/validator_arm/gen/arm32_decode_tests.cc
|
| index 088eecea02f3ca01133c1b3caa97693d28c5f98b..e430c9b3fbbe3bb148eb857a883393da890cefaa 100644
|
| --- a/src/trusted/validator_arm/gen/arm32_decode_tests.cc
|
| +++ b/src/trusted/validator_arm/gen/arm32_decode_tests.cc
|
| @@ -3192,10 +3192,10 @@ bool Binary2RegisterBitRangeNotRnIsPcTesterop1_24To20Is1111x_op2_7To5Isx10
|
| PassesParsePreconditions(inst, decoder);
|
| }
|
|
|
| -class Unary1RegisterSetTesterop2_6To4Is000_op_22To21Isx0
|
| +class Unary1RegisterSetTesterop2_6To4Is000_B_9Is0_op_22To21Isx0
|
| : public Unary1RegisterSetTester {
|
| public:
|
| - Unary1RegisterSetTesterop2_6To4Is000_op_22To21Isx0(const NamedClassDecoder& decoder)
|
| + Unary1RegisterSetTesterop2_6To4Is000_B_9Is0_op_22To21Isx0(const NamedClassDecoder& decoder)
|
| : Unary1RegisterSetTester(decoder) {}
|
| virtual bool PassesParsePreconditions(
|
| nacl_arm_dec::Instruction inst,
|
| @@ -3203,13 +3203,14 @@ class Unary1RegisterSetTesterop2_6To4Is000_op_22To21Isx0
|
|
|
| };
|
|
|
| -bool Unary1RegisterSetTesterop2_6To4Is000_op_22To21Isx0
|
| +bool Unary1RegisterSetTesterop2_6To4Is000_B_9Is0_op_22To21Isx0
|
| ::PassesParsePreconditions(
|
| nacl_arm_dec::Instruction inst,
|
| const NamedClassDecoder& decoder) {
|
|
|
| // Check that row patterns apply to pattern being checked.'
|
| if ((inst.Bits() & 0x00000070) != 0x00000000 /* op2(6:4) == ~000 */) return false;
|
| + if ((inst.Bits() & 0x00000200) != 0x00000000 /* B(9:9) == ~0 */) return false;
|
| if ((inst.Bits() & 0x00200000) != 0x00000000 /* op(22:21) == ~x0 */) return false;
|
|
|
| // Check other preconditions defined for the base decoder.
|
| @@ -3217,10 +3218,10 @@ bool Unary1RegisterSetTesterop2_6To4Is000_op_22To21Isx0
|
| PassesParsePreconditions(inst, decoder);
|
| }
|
|
|
| -class Unary1RegisterUseTesterop2_6To4Is000_op_22To21Is01_op1_19To16Isxx00
|
| +class Unary1RegisterUseTesterop2_6To4Is000_B_9Is0_op_22To21Is01_op1_19To16Isxx00
|
| : public Unary1RegisterUseTester {
|
| public:
|
| - Unary1RegisterUseTesterop2_6To4Is000_op_22To21Is01_op1_19To16Isxx00(const NamedClassDecoder& decoder)
|
| + Unary1RegisterUseTesterop2_6To4Is000_B_9Is0_op_22To21Is01_op1_19To16Isxx00(const NamedClassDecoder& decoder)
|
| : Unary1RegisterUseTester(decoder) {}
|
| virtual bool PassesParsePreconditions(
|
| nacl_arm_dec::Instruction inst,
|
| @@ -3228,13 +3229,14 @@ class Unary1RegisterUseTesterop2_6To4Is000_op_22To21Is01_op1_19To16Isxx00
|
|
|
| };
|
|
|
| -bool Unary1RegisterUseTesterop2_6To4Is000_op_22To21Is01_op1_19To16Isxx00
|
| +bool Unary1RegisterUseTesterop2_6To4Is000_B_9Is0_op_22To21Is01_op1_19To16Isxx00
|
| ::PassesParsePreconditions(
|
| nacl_arm_dec::Instruction inst,
|
| const NamedClassDecoder& decoder) {
|
|
|
| // Check that row patterns apply to pattern being checked.'
|
| if ((inst.Bits() & 0x00000070) != 0x00000000 /* op2(6:4) == ~000 */) return false;
|
| + if ((inst.Bits() & 0x00000200) != 0x00000000 /* B(9:9) == ~0 */) return false;
|
| if ((inst.Bits() & 0x00600000) != 0x00200000 /* op(22:21) == ~01 */) return false;
|
| if ((inst.Bits() & 0x00030000) != 0x00000000 /* op1(19:16) == ~xx00 */) return false;
|
|
|
| @@ -3243,10 +3245,10 @@ bool Unary1RegisterUseTesterop2_6To4Is000_op_22To21Is01_op1_19To16Isxx00
|
| PassesParsePreconditions(inst, decoder);
|
| }
|
|
|
| -class UnsafeCondNopTesterop2_6To4Is000_op_22To21Is01_op1_19To16Isxx01
|
| +class UnsafeCondNopTesterop2_6To4Is000_B_9Is0_op_22To21Is01_op1_19To16Isxx01
|
| : public UnsafeCondNopTester {
|
| public:
|
| - UnsafeCondNopTesterop2_6To4Is000_op_22To21Is01_op1_19To16Isxx01(const NamedClassDecoder& decoder)
|
| + UnsafeCondNopTesterop2_6To4Is000_B_9Is0_op_22To21Is01_op1_19To16Isxx01(const NamedClassDecoder& decoder)
|
| : UnsafeCondNopTester(decoder) {}
|
| virtual bool PassesParsePreconditions(
|
| nacl_arm_dec::Instruction inst,
|
| @@ -3254,13 +3256,14 @@ class UnsafeCondNopTesterop2_6To4Is000_op_22To21Is01_op1_19To16Isxx01
|
|
|
| };
|
|
|
| -bool UnsafeCondNopTesterop2_6To4Is000_op_22To21Is01_op1_19To16Isxx01
|
| +bool UnsafeCondNopTesterop2_6To4Is000_B_9Is0_op_22To21Is01_op1_19To16Isxx01
|
| ::PassesParsePreconditions(
|
| nacl_arm_dec::Instruction inst,
|
| const NamedClassDecoder& decoder) {
|
|
|
| // Check that row patterns apply to pattern being checked.'
|
| if ((inst.Bits() & 0x00000070) != 0x00000000 /* op2(6:4) == ~000 */) return false;
|
| + if ((inst.Bits() & 0x00000200) != 0x00000000 /* B(9:9) == ~0 */) return false;
|
| if ((inst.Bits() & 0x00600000) != 0x00200000 /* op(22:21) == ~01 */) return false;
|
| if ((inst.Bits() & 0x00030000) != 0x00010000 /* op1(19:16) == ~xx01 */) return false;
|
|
|
| @@ -3269,10 +3272,10 @@ bool UnsafeCondNopTesterop2_6To4Is000_op_22To21Is01_op1_19To16Isxx01
|
| PassesParsePreconditions(inst, decoder);
|
| }
|
|
|
| -class UnsafeCondNopTesterop2_6To4Is000_op_22To21Is01_op1_19To16Isxx1x
|
| +class UnsafeCondNopTesterop2_6To4Is000_B_9Is0_op_22To21Is01_op1_19To16Isxx1x
|
| : public UnsafeCondNopTester {
|
| public:
|
| - UnsafeCondNopTesterop2_6To4Is000_op_22To21Is01_op1_19To16Isxx1x(const NamedClassDecoder& decoder)
|
| + UnsafeCondNopTesterop2_6To4Is000_B_9Is0_op_22To21Is01_op1_19To16Isxx1x(const NamedClassDecoder& decoder)
|
| : UnsafeCondNopTester(decoder) {}
|
| virtual bool PassesParsePreconditions(
|
| nacl_arm_dec::Instruction inst,
|
| @@ -3280,13 +3283,14 @@ class UnsafeCondNopTesterop2_6To4Is000_op_22To21Is01_op1_19To16Isxx1x
|
|
|
| };
|
|
|
| -bool UnsafeCondNopTesterop2_6To4Is000_op_22To21Is01_op1_19To16Isxx1x
|
| +bool UnsafeCondNopTesterop2_6To4Is000_B_9Is0_op_22To21Is01_op1_19To16Isxx1x
|
| ::PassesParsePreconditions(
|
| nacl_arm_dec::Instruction inst,
|
| const NamedClassDecoder& decoder) {
|
|
|
| // Check that row patterns apply to pattern being checked.'
|
| if ((inst.Bits() & 0x00000070) != 0x00000000 /* op2(6:4) == ~000 */) return false;
|
| + if ((inst.Bits() & 0x00000200) != 0x00000000 /* B(9:9) == ~0 */) return false;
|
| if ((inst.Bits() & 0x00600000) != 0x00200000 /* op(22:21) == ~01 */) return false;
|
| if ((inst.Bits() & 0x00020000) != 0x00020000 /* op1(19:16) == ~xx1x */) return false;
|
|
|
| @@ -3295,10 +3299,10 @@ bool UnsafeCondNopTesterop2_6To4Is000_op_22To21Is01_op1_19To16Isxx1x
|
| PassesParsePreconditions(inst, decoder);
|
| }
|
|
|
| -class UnsafeCondNopTesterop2_6To4Is000_op_22To21Is11
|
| +class UnsafeCondNopTesterop2_6To4Is000_B_9Is0_op_22To21Is11
|
| : public UnsafeCondNopTester {
|
| public:
|
| - UnsafeCondNopTesterop2_6To4Is000_op_22To21Is11(const NamedClassDecoder& decoder)
|
| + UnsafeCondNopTesterop2_6To4Is000_B_9Is0_op_22To21Is11(const NamedClassDecoder& decoder)
|
| : UnsafeCondNopTester(decoder) {}
|
| virtual bool PassesParsePreconditions(
|
| nacl_arm_dec::Instruction inst,
|
| @@ -3306,13 +3310,14 @@ class UnsafeCondNopTesterop2_6To4Is000_op_22To21Is11
|
|
|
| };
|
|
|
| -bool UnsafeCondNopTesterop2_6To4Is000_op_22To21Is11
|
| +bool UnsafeCondNopTesterop2_6To4Is000_B_9Is0_op_22To21Is11
|
| ::PassesParsePreconditions(
|
| nacl_arm_dec::Instruction inst,
|
| const NamedClassDecoder& decoder) {
|
|
|
| // Check that row patterns apply to pattern being checked.'
|
| if ((inst.Bits() & 0x00000070) != 0x00000000 /* op2(6:4) == ~000 */) return false;
|
| + if ((inst.Bits() & 0x00000200) != 0x00000000 /* B(9:9) == ~0 */) return false;
|
| if ((inst.Bits() & 0x00600000) != 0x00600000 /* op(22:21) == ~11 */) return false;
|
|
|
| // Check other preconditions defined for the base decoder.
|
| @@ -3626,6 +3631,56 @@ bool CondNopTesterop_22Is0_op1_19To16Is0000_op2_7To0Is1111xxxx
|
| PassesParsePreconditions(inst, decoder);
|
| }
|
|
|
| +class MoveImmediate12ToApsrTesterop_22Is0_op1_19To16Is0100
|
| + : public MoveImmediate12ToApsrTester {
|
| + public:
|
| + MoveImmediate12ToApsrTesterop_22Is0_op1_19To16Is0100(const NamedClassDecoder& decoder)
|
| + : MoveImmediate12ToApsrTester(decoder) {}
|
| + virtual bool PassesParsePreconditions(
|
| + nacl_arm_dec::Instruction inst,
|
| + const NamedClassDecoder& decoder);
|
| +
|
| +};
|
| +
|
| +bool MoveImmediate12ToApsrTesterop_22Is0_op1_19To16Is0100
|
| +::PassesParsePreconditions(
|
| + nacl_arm_dec::Instruction inst,
|
| + const NamedClassDecoder& decoder) {
|
| +
|
| + // Check that row patterns apply to pattern being checked.'
|
| + if ((inst.Bits() & 0x00400000) != 0x00000000 /* op(22:22) == ~0 */) return false;
|
| + if ((inst.Bits() & 0x000F0000) != 0x00040000 /* op1(19:16) == ~0100 */) return false;
|
| +
|
| + // Check other preconditions defined for the base decoder.
|
| + return MoveImmediate12ToApsrTester::
|
| + PassesParsePreconditions(inst, decoder);
|
| +}
|
| +
|
| +class MoveImmediate12ToApsrTesterop_22Is0_op1_19To16Is1x00
|
| + : public MoveImmediate12ToApsrTester {
|
| + public:
|
| + MoveImmediate12ToApsrTesterop_22Is0_op1_19To16Is1x00(const NamedClassDecoder& decoder)
|
| + : MoveImmediate12ToApsrTester(decoder) {}
|
| + virtual bool PassesParsePreconditions(
|
| + nacl_arm_dec::Instruction inst,
|
| + const NamedClassDecoder& decoder);
|
| +
|
| +};
|
| +
|
| +bool MoveImmediate12ToApsrTesterop_22Is0_op1_19To16Is1x00
|
| +::PassesParsePreconditions(
|
| + nacl_arm_dec::Instruction inst,
|
| + const NamedClassDecoder& decoder) {
|
| +
|
| + // Check that row patterns apply to pattern being checked.'
|
| + if ((inst.Bits() & 0x00400000) != 0x00000000 /* op(22:22) == ~0 */) return false;
|
| + if ((inst.Bits() & 0x000B0000) != 0x00080000 /* op1(19:16) == ~1x00 */) return false;
|
| +
|
| + // Check other preconditions defined for the base decoder.
|
| + return MoveImmediate12ToApsrTester::
|
| + PassesParsePreconditions(inst, decoder);
|
| +}
|
| +
|
| class UnsafeCondNopTesterop_22Is0_op1_19To16Isxx01
|
| : public UnsafeCondNopTester {
|
| public:
|
| @@ -7085,47 +7140,47 @@ class Binary2RegisterBitRangeNotRnIsPcTester_op1_24To20Is1111x_op2_7To5Isx10_Ubf
|
| {}
|
| };
|
|
|
| -class Unary1RegisterSetTester_op2_6To4Is000_op_22To21Isx0_Mrs_Rule_102_A1_P206_Or_B6_10
|
| - : public Unary1RegisterSetTesterop2_6To4Is000_op_22To21Isx0 {
|
| +class Unary1RegisterSetTester_op2_6To4Is000_B_9Is0_op_22To21Isx0_Mrs_Rule_102_A1_P206_Or_B6_10
|
| + : public Unary1RegisterSetTesterop2_6To4Is000_B_9Is0_op_22To21Isx0 {
|
| public:
|
| - Unary1RegisterSetTester_op2_6To4Is000_op_22To21Isx0_Mrs_Rule_102_A1_P206_Or_B6_10()
|
| - : Unary1RegisterSetTesterop2_6To4Is000_op_22To21Isx0(
|
| + Unary1RegisterSetTester_op2_6To4Is000_B_9Is0_op_22To21Isx0_Mrs_Rule_102_A1_P206_Or_B6_10()
|
| + : Unary1RegisterSetTesterop2_6To4Is000_B_9Is0_op_22To21Isx0(
|
| state_.Unary1RegisterSet_Mrs_Rule_102_A1_P206_Or_B6_10_instance_)
|
| {}
|
| };
|
|
|
| -class Unary1RegisterUseTester_op2_6To4Is000_op_22To21Is01_op1_19To16Isxx00_Msr_Rule_104_A1_P210
|
| - : public Unary1RegisterUseTesterop2_6To4Is000_op_22To21Is01_op1_19To16Isxx00 {
|
| +class Unary1RegisterUseTester_op2_6To4Is000_B_9Is0_op_22To21Is01_op1_19To16Isxx00_Msr_Rule_104_A1_P210
|
| + : public Unary1RegisterUseTesterop2_6To4Is000_B_9Is0_op_22To21Is01_op1_19To16Isxx00 {
|
| public:
|
| - Unary1RegisterUseTester_op2_6To4Is000_op_22To21Is01_op1_19To16Isxx00_Msr_Rule_104_A1_P210()
|
| - : Unary1RegisterUseTesterop2_6To4Is000_op_22To21Is01_op1_19To16Isxx00(
|
| + Unary1RegisterUseTester_op2_6To4Is000_B_9Is0_op_22To21Is01_op1_19To16Isxx00_Msr_Rule_104_A1_P210()
|
| + : Unary1RegisterUseTesterop2_6To4Is000_B_9Is0_op_22To21Is01_op1_19To16Isxx00(
|
| state_.Unary1RegisterUse_Msr_Rule_104_A1_P210_instance_)
|
| {}
|
| };
|
|
|
| -class ForbiddenCondNopTester_op2_6To4Is000_op_22To21Is01_op1_19To16Isxx01_Msr_Rule_B6_1_7_P14
|
| - : public UnsafeCondNopTesterop2_6To4Is000_op_22To21Is01_op1_19To16Isxx01 {
|
| +class ForbiddenCondNopTester_op2_6To4Is000_B_9Is0_op_22To21Is01_op1_19To16Isxx01_Msr_Rule_B6_1_7_P14
|
| + : public UnsafeCondNopTesterop2_6To4Is000_B_9Is0_op_22To21Is01_op1_19To16Isxx01 {
|
| public:
|
| - ForbiddenCondNopTester_op2_6To4Is000_op_22To21Is01_op1_19To16Isxx01_Msr_Rule_B6_1_7_P14()
|
| - : UnsafeCondNopTesterop2_6To4Is000_op_22To21Is01_op1_19To16Isxx01(
|
| + ForbiddenCondNopTester_op2_6To4Is000_B_9Is0_op_22To21Is01_op1_19To16Isxx01_Msr_Rule_B6_1_7_P14()
|
| + : UnsafeCondNopTesterop2_6To4Is000_B_9Is0_op_22To21Is01_op1_19To16Isxx01(
|
| state_.ForbiddenCondNop_Msr_Rule_B6_1_7_P14_instance_)
|
| {}
|
| };
|
|
|
| -class ForbiddenCondNopTester_op2_6To4Is000_op_22To21Is01_op1_19To16Isxx1x_Msr_Rule_B6_1_7_P14
|
| - : public UnsafeCondNopTesterop2_6To4Is000_op_22To21Is01_op1_19To16Isxx1x {
|
| +class ForbiddenCondNopTester_op2_6To4Is000_B_9Is0_op_22To21Is01_op1_19To16Isxx1x_Msr_Rule_B6_1_7_P14
|
| + : public UnsafeCondNopTesterop2_6To4Is000_B_9Is0_op_22To21Is01_op1_19To16Isxx1x {
|
| public:
|
| - ForbiddenCondNopTester_op2_6To4Is000_op_22To21Is01_op1_19To16Isxx1x_Msr_Rule_B6_1_7_P14()
|
| - : UnsafeCondNopTesterop2_6To4Is000_op_22To21Is01_op1_19To16Isxx1x(
|
| + ForbiddenCondNopTester_op2_6To4Is000_B_9Is0_op_22To21Is01_op1_19To16Isxx1x_Msr_Rule_B6_1_7_P14()
|
| + : UnsafeCondNopTesterop2_6To4Is000_B_9Is0_op_22To21Is01_op1_19To16Isxx1x(
|
| state_.ForbiddenCondNop_Msr_Rule_B6_1_7_P14_instance_)
|
| {}
|
| };
|
|
|
| -class ForbiddenCondNopTester_op2_6To4Is000_op_22To21Is11_Msr_Rule_B6_1_7_P14
|
| - : public UnsafeCondNopTesterop2_6To4Is000_op_22To21Is11 {
|
| +class ForbiddenCondNopTester_op2_6To4Is000_B_9Is0_op_22To21Is11_Msr_Rule_B6_1_7_P14
|
| + : public UnsafeCondNopTesterop2_6To4Is000_B_9Is0_op_22To21Is11 {
|
| public:
|
| - ForbiddenCondNopTester_op2_6To4Is000_op_22To21Is11_Msr_Rule_B6_1_7_P14()
|
| - : UnsafeCondNopTesterop2_6To4Is000_op_22To21Is11(
|
| + ForbiddenCondNopTester_op2_6To4Is000_B_9Is0_op_22To21Is11_Msr_Rule_B6_1_7_P14()
|
| + : UnsafeCondNopTesterop2_6To4Is000_B_9Is0_op_22To21Is11(
|
| state_.ForbiddenCondNop_Msr_Rule_B6_1_7_P14_instance_)
|
| {}
|
| };
|
| @@ -7238,6 +7293,24 @@ class CondNopTester_op_22Is0_op1_19To16Is0000_op2_7To0Is1111xxxx_Dbg_Rule_40_A1_
|
| {}
|
| };
|
|
|
| +class MoveImmediate12ToApsrTester_op_22Is0_op1_19To16Is0100_Msr_Rule_103_A1_P208
|
| + : public MoveImmediate12ToApsrTesterop_22Is0_op1_19To16Is0100 {
|
| + public:
|
| + MoveImmediate12ToApsrTester_op_22Is0_op1_19To16Is0100_Msr_Rule_103_A1_P208()
|
| + : MoveImmediate12ToApsrTesterop_22Is0_op1_19To16Is0100(
|
| + state_.MoveImmediate12ToApsr_Msr_Rule_103_A1_P208_instance_)
|
| + {}
|
| +};
|
| +
|
| +class MoveImmediate12ToApsrTester_op_22Is0_op1_19To16Is1x00_Msr_Rule_103_A1_P208
|
| + : public MoveImmediate12ToApsrTesterop_22Is0_op1_19To16Is1x00 {
|
| + public:
|
| + MoveImmediate12ToApsrTester_op_22Is0_op1_19To16Is1x00_Msr_Rule_103_A1_P208()
|
| + : MoveImmediate12ToApsrTesterop_22Is0_op1_19To16Is1x00(
|
| + state_.MoveImmediate12ToApsr_Msr_Rule_103_A1_P208_instance_)
|
| + {}
|
| +};
|
| +
|
| class ForbiddenCondNopTester_op_22Is0_op1_19To16Isxx01_Msr_Rule_B6_1_6_A1_PB6_12
|
| : public UnsafeCondNopTesterop_22Is0_op1_19To16Isxx01 {
|
| public:
|
| @@ -9068,36 +9141,36 @@ TEST_F(Arm32DecoderStateTests,
|
| }
|
|
|
| TEST_F(Arm32DecoderStateTests,
|
| - Unary1RegisterSetTester_op2_6To4Is000_op_22To21Isx0_Mrs_Rule_102_A1_P206_Or_B6_10_cccc00010r001111dddd000000000000_Test) {
|
| - Unary1RegisterSetTester_op2_6To4Is000_op_22To21Isx0_Mrs_Rule_102_A1_P206_Or_B6_10 tester;
|
| + Unary1RegisterSetTester_op2_6To4Is000_B_9Is0_op_22To21Isx0_Mrs_Rule_102_A1_P206_Or_B6_10_cccc00010r001111dddd000000000000_Test) {
|
| + Unary1RegisterSetTester_op2_6To4Is000_B_9Is0_op_22To21Isx0_Mrs_Rule_102_A1_P206_Or_B6_10 tester;
|
| tester.Test("cccc00010r001111dddd000000000000");
|
| }
|
|
|
| TEST_F(Arm32DecoderStateTests,
|
| - Unary1RegisterUseTester_op2_6To4Is000_op_22To21Is01_op1_19To16Isxx00_Msr_Rule_104_A1_P210_cccc00010010mm00111100000000nnnn_Test) {
|
| - Unary1RegisterUseTester_op2_6To4Is000_op_22To21Is01_op1_19To16Isxx00_Msr_Rule_104_A1_P210 tester;
|
| + Unary1RegisterUseTester_op2_6To4Is000_B_9Is0_op_22To21Is01_op1_19To16Isxx00_Msr_Rule_104_A1_P210_cccc00010010mm00111100000000nnnn_Test) {
|
| + Unary1RegisterUseTester_op2_6To4Is000_B_9Is0_op_22To21Is01_op1_19To16Isxx00_Msr_Rule_104_A1_P210 tester;
|
| tester.Test("cccc00010010mm00111100000000nnnn");
|
| }
|
|
|
| TEST_F(Arm32DecoderStateTests,
|
| - ForbiddenCondNopTester_op2_6To4Is000_op_22To21Is01_op1_19To16Isxx01_Msr_Rule_B6_1_7_P14_cccc00010010mm01111100000000nnnn_Test) {
|
| - ForbiddenCondNopTester_op2_6To4Is000_op_22To21Is01_op1_19To16Isxx01_Msr_Rule_B6_1_7_P14 baseline_tester;
|
| + ForbiddenCondNopTester_op2_6To4Is000_B_9Is0_op_22To21Is01_op1_19To16Isxx01_Msr_Rule_B6_1_7_P14_cccc00010010mm01111100000000nnnn_Test) {
|
| + ForbiddenCondNopTester_op2_6To4Is000_B_9Is0_op_22To21Is01_op1_19To16Isxx01_Msr_Rule_B6_1_7_P14 baseline_tester;
|
| NamedForbidden_Msr_Rule_B6_1_7_P14 actual;
|
| ActualVsBaselineTester a_vs_b_tester(actual, baseline_tester);
|
| a_vs_b_tester.Test("cccc00010010mm01111100000000nnnn");
|
| }
|
|
|
| TEST_F(Arm32DecoderStateTests,
|
| - ForbiddenCondNopTester_op2_6To4Is000_op_22To21Is01_op1_19To16Isxx1x_Msr_Rule_B6_1_7_P14_cccc00010010mm1m111100000000nnnn_Test) {
|
| - ForbiddenCondNopTester_op2_6To4Is000_op_22To21Is01_op1_19To16Isxx1x_Msr_Rule_B6_1_7_P14 baseline_tester;
|
| + ForbiddenCondNopTester_op2_6To4Is000_B_9Is0_op_22To21Is01_op1_19To16Isxx1x_Msr_Rule_B6_1_7_P14_cccc00010010mm1m111100000000nnnn_Test) {
|
| + ForbiddenCondNopTester_op2_6To4Is000_B_9Is0_op_22To21Is01_op1_19To16Isxx1x_Msr_Rule_B6_1_7_P14 baseline_tester;
|
| NamedForbidden_Msr_Rule_B6_1_7_P14 actual;
|
| ActualVsBaselineTester a_vs_b_tester(actual, baseline_tester);
|
| a_vs_b_tester.Test("cccc00010010mm1m111100000000nnnn");
|
| }
|
|
|
| TEST_F(Arm32DecoderStateTests,
|
| - ForbiddenCondNopTester_op2_6To4Is000_op_22To21Is11_Msr_Rule_B6_1_7_P14_cccc00010110mmmm111100000000nnnn_Test) {
|
| - ForbiddenCondNopTester_op2_6To4Is000_op_22To21Is11_Msr_Rule_B6_1_7_P14 baseline_tester;
|
| + ForbiddenCondNopTester_op2_6To4Is000_B_9Is0_op_22To21Is11_Msr_Rule_B6_1_7_P14_cccc00010110mmmm111100000000nnnn_Test) {
|
| + ForbiddenCondNopTester_op2_6To4Is000_B_9Is0_op_22To21Is11_Msr_Rule_B6_1_7_P14 baseline_tester;
|
| NamedForbidden_Msr_Rule_B6_1_7_P14 actual;
|
| ActualVsBaselineTester a_vs_b_tester(actual, baseline_tester);
|
| a_vs_b_tester.Test("cccc00010110mmmm111100000000nnnn");
|
| @@ -9144,11 +9217,11 @@ TEST_F(Arm32DecoderStateTests,
|
| }
|
|
|
| TEST_F(Arm32DecoderStateTests,
|
| - ForbiddenCondNopTester_op2_6To4Is111_op_22To21Is11_Smc_Rule_B6_1_9_P18_cccc000101100000000000000111mmmm_Test) {
|
| + ForbiddenCondNopTester_op2_6To4Is111_op_22To21Is11_Smc_Rule_B6_1_9_P18_cccc000101100000000000000111iiii_Test) {
|
| ForbiddenCondNopTester_op2_6To4Is111_op_22To21Is11_Smc_Rule_B6_1_9_P18 baseline_tester;
|
| NamedForbidden_Smc_Rule_B6_1_9_P18 actual;
|
| ActualVsBaselineTester a_vs_b_tester(actual, baseline_tester);
|
| - a_vs_b_tester.Test("cccc000101100000000000000111mmmm");
|
| + a_vs_b_tester.Test("cccc000101100000000000000111iiii");
|
| }
|
|
|
| TEST_F(Arm32DecoderStateTests,
|
| @@ -9200,6 +9273,22 @@ TEST_F(Arm32DecoderStateTests,
|
| }
|
|
|
| TEST_F(Arm32DecoderStateTests,
|
| + MoveImmediate12ToApsrTester_op_22Is0_op1_19To16Is0100_Msr_Rule_103_A1_P208_cccc0011001001001111iiiiiiiiiiii_Test) {
|
| + MoveImmediate12ToApsrTester_op_22Is0_op1_19To16Is0100_Msr_Rule_103_A1_P208 baseline_tester;
|
| + NamedDontCareInst_Msr_Rule_103_A1_P208 actual;
|
| + ActualVsBaselineTester a_vs_b_tester(actual, baseline_tester);
|
| + a_vs_b_tester.Test("cccc0011001001001111iiiiiiiiiiii");
|
| +}
|
| +
|
| +TEST_F(Arm32DecoderStateTests,
|
| + MoveImmediate12ToApsrTester_op_22Is0_op1_19To16Is1x00_Msr_Rule_103_A1_P208_cccc001100101x001111iiiiiiiiiiii_Test) {
|
| + MoveImmediate12ToApsrTester_op_22Is0_op1_19To16Is1x00_Msr_Rule_103_A1_P208 baseline_tester;
|
| + NamedDontCareInst_Msr_Rule_103_A1_P208 actual;
|
| + ActualVsBaselineTester a_vs_b_tester(actual, baseline_tester);
|
| + a_vs_b_tester.Test("cccc001100101x001111iiiiiiiiiiii");
|
| +}
|
| +
|
| +TEST_F(Arm32DecoderStateTests,
|
| ForbiddenCondNopTester_op_22Is0_op1_19To16Isxx01_Msr_Rule_B6_1_6_A1_PB6_12_cccc00110010ii011111iiiiiiiiiiii_Test) {
|
| ForbiddenCondNopTester_op_22Is0_op1_19To16Isxx01_Msr_Rule_B6_1_6_A1_PB6_12 baseline_tester;
|
| NamedForbidden_Msr_Rule_B6_1_6_A1_PB6_12 actual;
|
| @@ -9848,11 +9937,11 @@ TEST_F(Arm32DecoderStateTests,
|
| }
|
|
|
| TEST_F(Arm32DecoderStateTests,
|
| - LoadExclusive2RegisterOpTester_op_23To20Is1101_Ldrexb_Rule_70_A1_P144_cccc00011101nnnndddd111110011111_Test) {
|
| + LoadExclusive2RegisterOpTester_op_23To20Is1101_Ldrexb_Rule_70_A1_P144_cccc00011101nnnntttt111110011111_Test) {
|
| LoadExclusive2RegisterOpTester_op_23To20Is1101_Ldrexb_Rule_70_A1_P144 baseline_tester;
|
| NamedLoadBasedMemory_Ldrexb_Rule_70_A1_P144 actual;
|
| ActualVsBaselineTester a_vs_b_tester(actual, baseline_tester);
|
| - a_vs_b_tester.Test("cccc00011101nnnndddd111110011111");
|
| + a_vs_b_tester.Test("cccc00011101nnnntttt111110011111");
|
| }
|
|
|
| TEST_F(Arm32DecoderStateTests,
|
|
|