Remove the llvm.nacl.thread.stack.padding intrinsic

lib/Target/Mips/MipsISelLowering.cpp

Index: lib/Target/Mips/MipsISelLowering.cpp
diff --git a/lib/Target/Mips/MipsISelLowering.cpp b/lib/Target/Mips/MipsISelLowering.cpp
index bc0a616e330c6a173bcf980063351d17b1436d14..efb15ecc34f96aa2094671e7dba9eb893ba1c00f 100644
--- a/lib/Target/Mips/MipsISelLowering.cpp
+++ b/lib/Target/Mips/MipsISelLowering.cpp
@@ -290,7 +290,6 @@ MipsTargetLowering(MipsTargetMachine &TM)
 
   // @LOCALMOD-BEGIN
   if (Subtarget->isTargetNaCl()) {
-    setOperationAction(ISD::NACL_THREAD_STACK_PADDING, MVT::i32, Custom);
     setOperationAction(ISD::NACL_TP_ALIGN,             MVT::i32, Custom);
     setOperationAction(ISD::NACL_TP_TLS_OFFSET,        MVT::i32, Custom);
     setOperationAction(ISD::NACL_TP_TDB_OFFSET,        MVT::i32, Custom);
@@ -824,8 +823,6 @@ LowerOperation(SDValue Op, SelectionDAG &DAG) const
     case ISD::STORE:              return LowerSTORE(Op, DAG);
 
     // @LOCALMOD-BEGIN
-    case ISD::NACL_THREAD_STACK_PADDING:
-      return LowerNaClThreadStackPadding(Op, DAG);
     case ISD::NACL_TP_ALIGN:      return LowerNaClTpAlign(Op, DAG);
     case ISD::NACL_TP_TLS_OFFSET: return LowerNaClTpTlsOffset(Op, DAG);
     case ISD::NACL_TP_TDB_OFFSET: return LowerNaClTpTdbOffset(Op, DAG);
@@ -1687,11 +1684,6 @@ SDValue MipsTargetLowering::LowerBlockAddress(SDValue Op,
 // NaCl TLS setup / layout intrinsics.
 // See: native_client/src/untrusted/nacl/tls_params.h
 
-SDValue MipsTargetLowering::LowerNaClThreadStackPadding(SDValue Op,
-                                                      SelectionDAG &DAG) const {
-  return DAG.getConstant(0, Op.getValueType().getSimpleVT());
-}
-
 SDValue MipsTargetLowering::LowerNaClTpAlign(SDValue Op,
                                              SelectionDAG &DAG) const {
   return DAG.getConstant(4, Op.getValueType().getSimpleVT());