Remove the llvm.nacl.thread.stack.padding intrinsic

lib/Target/Mips/MipsISelLowering.cpp

 //===-- MipsISelLowering.cpp - Mips DAG Lowering Implementation -----------===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 //
 // This file defines the interfaces that Mips uses to lower LLVM code into a
@@ skipping 272 matching lines @@
 
   if (HasMips64) {
     setLoadExtAction(ISD::SEXTLOAD, MVT::i32, Custom);
     setLoadExtAction(ISD::ZEXTLOAD, MVT::i32, Custom);
     setLoadExtAction(ISD::EXTLOAD, MVT::i32, Custom);
     setTruncStoreAction(MVT::i64, MVT::i32, Custom);
   }
 
   // @LOCALMOD-BEGIN
   if (Subtarget->isTargetNaCl()) {
-    setOperationAction(ISD::NACL_THREAD_STACK_PADDING, MVT::i32, Custom);
     setOperationAction(ISD::NACL_TP_ALIGN,             MVT::i32, Custom);
     setOperationAction(ISD::NACL_TP_TLS_OFFSET,        MVT::i32, Custom);
     setOperationAction(ISD::NACL_TP_TDB_OFFSET,        MVT::i32, Custom);
   }
   // @LOCALMOD-END
 
   setTargetDAGCombine(ISD::ADDE);
   setTargetDAGCombine(ISD::SUBE);
   setTargetDAGCombine(ISD::SDIVREM);
   setTargetDAGCombine(ISD::UDIVREM);
@@ skipping 513 matching lines @@
     case ISD::FRAMEADDR:          return LowerFRAMEADDR(Op, DAG);
     case ISD::MEMBARRIER:         return LowerMEMBARRIER(Op, DAG);
     case ISD::ATOMIC_FENCE:       return LowerATOMIC_FENCE(Op, DAG);
     case ISD::SHL_PARTS:          return LowerShiftLeftParts(Op, DAG);
     case ISD::SRA_PARTS:          return LowerShiftRightParts(Op, DAG, true);
     case ISD::SRL_PARTS:          return LowerShiftRightParts(Op, DAG, false);
     case ISD::LOAD:               return LowerLOAD(Op, DAG);
     case ISD::STORE:              return LowerSTORE(Op, DAG);
 
     // @LOCALMOD-BEGIN
-    case ISD::NACL_THREAD_STACK_PADDING:
-      return LowerNaClThreadStackPadding(Op, DAG);
     case ISD::NACL_TP_ALIGN:      return LowerNaClTpAlign(Op, DAG);
     case ISD::NACL_TP_TLS_OFFSET: return LowerNaClTpTlsOffset(Op, DAG);
     case ISD::NACL_TP_TDB_OFFSET: return LowerNaClTpTdbOffset(Op, DAG);
     // @LOCALMOD-END
   }
   return SDValue();
 }
 
 //===----------------------------------------------------------------------===//
 //  Lower helper functions
@@ skipping 841 matching lines @@
                              MachinePointerInfo(), false, false, false, 0);
   SDValue Lo = DAG.getNode(MipsISD::Lo, dl, ValTy, BALOOffset);
   return DAG.getNode(ISD::ADD, dl, ValTy, Load, Lo);
 }
 
 // @LOCALMOD-BEGIN
 
 // NaCl TLS setup / layout intrinsics.
 // See: native_client/src/untrusted/nacl/tls_params.h
 
-SDValue MipsTargetLowering::LowerNaClThreadStackPadding(SDValue Op,
-                                                      SelectionDAG &DAG) const {
-  return DAG.getConstant(0, Op.getValueType().getSimpleVT());
-}
-
 SDValue MipsTargetLowering::LowerNaClTpAlign(SDValue Op,
                                              SelectionDAG &DAG) const {
   return DAG.getConstant(4, Op.getValueType().getSimpleVT());
 }
 
 SDValue MipsTargetLowering::LowerNaClTpTlsOffset(SDValue Op,
                                                  SelectionDAG &DAG) const {
   return DAG.getConstant(0, Op.getValueType().getSimpleVT());
 }
 
@@ skipping 1875 matching lines @@
     return false;
   return Imm.isZero();
 }
 
 unsigned MipsTargetLowering::getJumpTableEncoding() const {
   if (IsN64)
     return MachineJumpTableInfo::EK_GPRel64BlockAddress;
 
   return TargetLowering::getJumpTableEncoding();
 }