Remove the llvm.nacl.thread.stack.padding intrinsic

lib/Target/ARM/ARMISelLowering.cpp

Index: lib/Target/ARM/ARMISelLowering.cpp
diff --git a/lib/Target/ARM/ARMISelLowering.cpp b/lib/Target/ARM/ARMISelLowering.cpp
index 238b79e1f1e5a9c0cfa7d9dec137b0fd7d697350..ea0f5d1f1d9f66c2d511bdaa2ad591ede62f8b21 100644
--- a/lib/Target/ARM/ARMISelLowering.cpp
+++ b/lib/Target/ARM/ARMISelLowering.cpp
@@ -821,7 +821,6 @@ ARMTargetLowering::ARMTargetLowering(TargetMachine &TM)
 
   // @LOCALMOD-BEGIN
   if (Subtarget->isTargetNaCl()) {
-    setOperationAction(ISD::NACL_THREAD_STACK_PADDING, MVT::i32, Custom);
     setOperationAction(ISD::NACL_TP_ALIGN,             MVT::i32, Custom);
     setOperationAction(ISD::NACL_TP_TLS_OFFSET,        MVT::i32, Custom);
     setOperationAction(ISD::NACL_TP_TDB_OFFSET,        MVT::i32, Custom);
@@ -2190,15 +2189,6 @@ SDValue ARMTargetLowering::LowerNaClTpTdbOffset(SDValue Op,
 }
 
 SDValue
-ARMTargetLowering::LowerNaClThreadStackPadding(SDValue Op,
-                                               SelectionDAG &DAG) const {
-  // size_t __nacl_thread_stack_padding () {
-  //   return 0;
-  // }
-  return DAG.getConstant(0, Op.getValueType().getSimpleVT());
-}
-
-SDValue
 ARMTargetLowering::LowerNaClTargetArch(SDValue Op, SelectionDAG &DAG) const {
   // size_t __nacl_target_arch () {
   //   return PnaclTargetArchitectureARM_32;
@@ -5505,8 +5495,6 @@ SDValue ARMTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
   case ISD::ATOMIC_LOAD:
   case ISD::ATOMIC_STORE:  return LowerAtomicLoadStore(Op, DAG);
   // @LOCALMOD-BEGIN
-  case ISD::NACL_THREAD_STACK_PADDING:
-    return LowerNaClThreadStackPadding(Op, DAG);
   case ISD::NACL_TP_ALIGN:         return LowerNaClTpAlign(Op, DAG);
   case ISD::NACL_TP_TLS_OFFSET:    return LowerNaClTpTlsOffset(Op, DAG);
   case ISD::NACL_TP_TDB_OFFSET:    return LowerNaClTpTdbOffset(Op, DAG);