Remove the llvm.nacl.thread.stack.padding intrinsic

lib/Target/ARM/ARMISelLowering.cpp

 //===-- ARMISelLowering.cpp - ARM DAG Lowering Implementation -------------===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 //
 // This file defines the interfaces that ARM uses to lower LLVM code into a
@@ skipping 803 matching lines @@
     }
     // Special handling for half-precision FP.
     if (!Subtarget->hasFP16()) {
       setOperationAction(ISD::FP16_TO_FP32, MVT::f32, Expand);
       setOperationAction(ISD::FP32_TO_FP16, MVT::i32, Expand);
     }
   }
 
   // @LOCALMOD-BEGIN
   if (Subtarget->isTargetNaCl()) {
-    setOperationAction(ISD::NACL_THREAD_STACK_PADDING, MVT::i32, Custom);
     setOperationAction(ISD::NACL_TP_ALIGN,             MVT::i32, Custom);
     setOperationAction(ISD::NACL_TP_TLS_OFFSET,        MVT::i32, Custom);
     setOperationAction(ISD::NACL_TP_TDB_OFFSET,        MVT::i32, Custom);
     setOperationAction(ISD::NACL_TARGET_ARCH,          MVT::i32, Custom);
   }
   // @LOCALMOD-END
 
   // We have target-specific dag combine patterns for the following nodes:
   // ARMISD::VMOVRRD  - No need to call setTargetDAGCombine
   setTargetDAGCombine(ISD::ADD);
@@ skipping 1348 matching lines @@
   // ssize_t __nacl_tp_tdb_offset (size_t tdb_size) {
   //   return -tdb_size;
   // }
   DebugLoc dl = Op.getDebugLoc();
   return DAG.getNode(ISD::SUB, dl, Op.getValueType().getSimpleVT(),
                      DAG.getConstant(0, Op.getValueType().getSimpleVT()),
                      Op.getOperand(0));
 }
 
 SDValue
-ARMTargetLowering::LowerNaClThreadStackPadding(SDValue Op,
-                                               SelectionDAG &DAG) const {
-  // size_t __nacl_thread_stack_padding () {
-  //   return 0;
-  // }
-  return DAG.getConstant(0, Op.getValueType().getSimpleVT());
-}
-
-SDValue
 ARMTargetLowering::LowerNaClTargetArch(SDValue Op, SelectionDAG &DAG) const {
   // size_t __nacl_target_arch () {
   //   return PnaclTargetArchitectureARM_32;
   // }
   return DAG.getConstant(PnaclTargetArchitectureARM_32,
                          Op.getValueType().getSimpleVT());
 }
 
 //////////////////////////////////////////////////////////////////////
 
@@ skipping 3286 matching lines @@
   case ISD::MUL:           return LowerMUL(Op, DAG);
   case ISD::SDIV:          return LowerSDIV(Op, DAG);
   case ISD::UDIV:          return LowerUDIV(Op, DAG);
   case ISD::ADDC:
   case ISD::ADDE:
   case ISD::SUBC:
   case ISD::SUBE:          return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
   case ISD::ATOMIC_LOAD:
   case ISD::ATOMIC_STORE:  return LowerAtomicLoadStore(Op, DAG);
   // @LOCALMOD-BEGIN
-  case ISD::NACL_THREAD_STACK_PADDING:
-    return LowerNaClThreadStackPadding(Op, DAG);
   case ISD::NACL_TP_ALIGN:         return LowerNaClTpAlign(Op, DAG);
   case ISD::NACL_TP_TLS_OFFSET:    return LowerNaClTpTlsOffset(Op, DAG);
   case ISD::NACL_TP_TDB_OFFSET:    return LowerNaClTpTdbOffset(Op, DAG);
   case ISD::NACL_TARGET_ARCH:      return LowerNaClTargetArch(Op, DAG);
   // @LOCALMOD-END
   }
 }
 
 /// ReplaceNodeResults - Replace the results of node with an illegal result
 /// type with new values built out of custom code.
@@ skipping 4469 matching lines @@
     Info.readMem = true;
     Info.writeMem = false;
     return true;
   }
   default:
     break;
   }
 
   return false;
 }