src/trusted/validator_arm/gen/arm32_decode_named_decoder.h - Issue 10459058: Define a baseline and testing patterns for ARM load_store_word_byte table.

Unified Diff: src/trusted/validator_arm/gen/arm32_decode_named_decoder.h

Issue 10459058: Define a baseline and testing patterns for ARM load_store_word_byte table. (Closed) Base URL: svn://svn.chromium.org/native_client/trunk/src/native_client/

Patch Set: Created 8 years, 6 months ago

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Index: src/trusted/validator_arm/gen/arm32_decode_named_decoder.h

===================================================================

--- src/trusted/validator_arm/gen/arm32_decode_named_decoder.h (revision 8812)

+++ src/trusted/validator_arm/gen/arm32_decode_named_decoder.h (working copy)

@@ -132,24 +132,28 @@

const NamedForbiddenCondNop_Sev_Rule_158_A1_P316 ForbiddenCondNop_Sev_Rule_158_A1_P316_instance_;

const NamedForbiddenCondNop_Wfe_Rule_411_A1_P808 ForbiddenCondNop_Wfe_Rule_411_A1_P808_instance_;

const NamedForbiddenCondNop_Wfi_Rule_412_A1_P810 ForbiddenCondNop_Wfi_Rule_412_A1_P810_instance_;

- const NamedLoad2RegisterImmediateDoubleOp_Ldrd_Rule_66_A1_P136 Load2RegisterImmediateDoubleOp_Ldrd_Rule_66_A1_P136_instance_;

- const NamedLoad2RegisterImmediateDoubleOp_Ldrd_Rule_67_A1_P138 Load2RegisterImmediateDoubleOp_Ldrd_Rule_67_A1_P138_instance_;

- const NamedLoad2RegisterImmediateOp_Ldrh_Rule_74_A1_P152 Load2RegisterImmediateOp_Ldrh_Rule_74_A1_P152_instance_;

- const NamedLoad2RegisterImmediateOp_Ldrh_Rule_75_A1_P154 Load2RegisterImmediateOp_Ldrh_Rule_75_A1_P154_instance_;

- const NamedLoad2RegisterImmediateOp_Ldrsb_Rule_78_A1_P160 Load2RegisterImmediateOp_Ldrsb_Rule_78_A1_P160_instance_;

- const NamedLoad2RegisterImmediateOp_Ldrsh_Rule_82_A1_P168 Load2RegisterImmediateOp_Ldrsh_Rule_82_A1_P168_instance_;

- const NamedLoad2RegisterImmediateOp_Ldrsh_Rule_83_A1_P170 Load2RegisterImmediateOp_Ldrsh_Rule_83_A1_P170_instance_;

- const NamedLoad2RegisterImmediateOp_ldrsb_Rule_79_A1_162 Load2RegisterImmediateOp_ldrsb_Rule_79_A1_162_instance_;

+ const NamedLoad2RegisterImm12Op_Ldr_Rule_58_A1_P120 Load2RegisterImm12Op_Ldr_Rule_58_A1_P120_instance_;

+ const NamedLoad2RegisterImm12Op_Ldr_Rule_59_A1_P122 Load2RegisterImm12Op_Ldr_Rule_59_A1_P122_instance_;

+ const NamedLoad2RegisterImm12Op_Ldrb_Rule_62_A1_P128 Load2RegisterImm12Op_Ldrb_Rule_62_A1_P128_instance_;

+ const NamedLoad2RegisterImm12Op_Ldrb_Rule_63_A1_P130 Load2RegisterImm12Op_Ldrb_Rule_63_A1_P130_instance_;

+ const NamedLoad2RegisterImm8DoubleOp_Ldrd_Rule_66_A1_P136 Load2RegisterImm8DoubleOp_Ldrd_Rule_66_A1_P136_instance_;

+ const NamedLoad2RegisterImm8DoubleOp_Ldrd_Rule_67_A1_P138 Load2RegisterImm8DoubleOp_Ldrd_Rule_67_A1_P138_instance_;

+ const NamedLoad2RegisterImm8Op_Ldrh_Rule_74_A1_P152 Load2RegisterImm8Op_Ldrh_Rule_74_A1_P152_instance_;

+ const NamedLoad2RegisterImm8Op_Ldrh_Rule_75_A1_P154 Load2RegisterImm8Op_Ldrh_Rule_75_A1_P154_instance_;

+ const NamedLoad2RegisterImm8Op_Ldrsb_Rule_78_A1_P160 Load2RegisterImm8Op_Ldrsb_Rule_78_A1_P160_instance_;

+ const NamedLoad2RegisterImm8Op_Ldrsh_Rule_82_A1_P168 Load2RegisterImm8Op_Ldrsh_Rule_82_A1_P168_instance_;

+ const NamedLoad2RegisterImm8Op_Ldrsh_Rule_83_A1_P170 Load2RegisterImm8Op_Ldrsh_Rule_83_A1_P170_instance_;

+ const NamedLoad2RegisterImm8Op_ldrsb_Rule_79_A1_162 Load2RegisterImm8Op_ldrsb_Rule_79_A1_162_instance_;

const NamedLoad3RegisterDoubleOp_Ldrd_Rule_68_A1_P140 Load3RegisterDoubleOp_Ldrd_Rule_68_A1_P140_instance_;

+ const NamedLoad3RegisterImm5Op_Ldr_Rule_60_A1_P124 Load3RegisterImm5Op_Ldr_Rule_60_A1_P124_instance_;

+ const NamedLoad3RegisterImm5Op_Ldrb_Rule_64_A1_P132 Load3RegisterImm5Op_Ldrb_Rule_64_A1_P132_instance_;

const NamedLoad3RegisterOp_Ldrh_Rule_76_A1_P156 Load3RegisterOp_Ldrh_Rule_76_A1_P156_instance_;

const NamedLoad3RegisterOp_Ldrsb_Rule_80_A1_P164 Load3RegisterOp_Ldrsb_Rule_80_A1_P164_instance_;

const NamedLoad3RegisterOp_Ldrsh_Rule_84_A1_P172 Load3RegisterOp_Ldrsh_Rule_84_A1_P172_instance_;

const NamedLoadCoprocessor_None LoadCoprocessor_None_instance_;

const NamedLoadDoubleExclusive_None LoadDoubleExclusive_None_instance_;

const NamedLoadExclusive_None LoadExclusive_None_instance_;

- const NamedLoadImmediate_None LoadImmediate_None_instance_;

const NamedLoadMultiple_None LoadMultiple_None_instance_;

- const NamedLoadRegister_None LoadRegister_None_instance_;

const NamedLongMultiply_None LongMultiply_None_instance_;

const NamedMaskedBinary2RegisterImmediateOp_Bic_Rule_19_A1_P50 MaskedBinary2RegisterImmediateOp_Bic_Rule_19_A1_P50_instance_;

const NamedMaskedBinaryRegisterImmediateTest_Tst_Rule_230_A1_P454 MaskedBinaryRegisterImmediateTest_Tst_Rule_230_A1_P454_instance_;

@@ -160,14 +164,17 @@

const NamedPackSatRev_None PackSatRev_None_instance_;

const NamedRoadblock_None Roadblock_None_instance_;

const NamedSatAddSub_None SatAddSub_None_instance_;

- const NamedStore2RegisterImmediateDoubleOp_Strd_Rule_200_A1_P396 Store2RegisterImmediateDoubleOp_Strd_Rule_200_A1_P396_instance_;

- const NamedStore2RegisterImmediateOp_Strh_Rule_207_A1_P410 Store2RegisterImmediateOp_Strh_Rule_207_A1_P410_instance_;

+ const NamedStore2RegisterImm12Op_Str_Rule_194_A1_P384 Store2RegisterImm12Op_Str_Rule_194_A1_P384_instance_;

+ const NamedStore2RegisterImm12Op_Strb_Rule_197_A1_P390 Store2RegisterImm12Op_Strb_Rule_197_A1_P390_instance_;

+ const NamedStore2RegisterImm8DoubleOp_Strd_Rule_200_A1_P396 Store2RegisterImm8DoubleOp_Strd_Rule_200_A1_P396_instance_;

+ const NamedStore2RegisterImm8Op_Strh_Rule_207_A1_P410 Store2RegisterImm8Op_Strh_Rule_207_A1_P410_instance_;

const NamedStore3RegisterDoubleOp_Strd_Rule_201_A1_P398 Store3RegisterDoubleOp_Strd_Rule_201_A1_P398_instance_;

+ const NamedStore3RegisterImm5Op_Str_Rule_195_A1_P386 Store3RegisterImm5Op_Str_Rule_195_A1_P386_instance_;

+ const NamedStore3RegisterImm5Op_Strb_Rule_198_A1_P392 Store3RegisterImm5Op_Strb_Rule_198_A1_P392_instance_;

const NamedStore3RegisterOp_Strh_Rule_208_A1_P412 Store3RegisterOp_Strh_Rule_208_A1_P412_instance_;

const NamedStoreCoprocessor_None StoreCoprocessor_None_instance_;

const NamedStoreExclusive_None StoreExclusive_None_instance_;

const NamedStoreImmediate_None StoreImmediate_None_instance_;

- const NamedStoreRegister_None StoreRegister_None_instance_;

const NamedUnary1RegisterBitRange_Bfc_17_A1_P46 Unary1RegisterBitRange_Bfc_17_A1_P46_instance_;

const NamedUnary1RegisterImmediateOp_Adr_Rule_10_A1_P32 Unary1RegisterImmediateOp_Adr_Rule_10_A1_P32_instance_;

const NamedUnary1RegisterImmediateOp_Adr_Rule_10_A2_P32 Unary1RegisterImmediateOp_Adr_Rule_10_A2_P32_instance_;

@@ -268,6 +275,10 @@

const NamedForbidden_Sev_Rule_158_A1_P316 Forbidden_Sev_Rule_158_A1_P316_instance_;

const NamedForbidden_Wfe_Rule_411_A1_P808 Forbidden_Wfe_Rule_411_A1_P808_instance_;

const NamedForbidden_Wfi_Rule_412_A1_P810 Forbidden_Wfi_Rule_412_A1_P810_instance_;

+ const NamedLdrImmediate_Ldr_Rule_58_A1_P120 LdrImmediate_Ldr_Rule_58_A1_P120_instance_;

+ const NamedLdrImmediate_Ldr_Rule_59_A1_P122 LdrImmediate_Ldr_Rule_59_A1_P122_instance_;

+ const NamedLdrImmediate_Ldrb_Rule_62_A1_P128 LdrImmediate_Ldrb_Rule_62_A1_P128_instance_;

+ const NamedLdrImmediate_Ldrb_Rule_63_A1_P130 LdrImmediate_Ldrb_Rule_63_A1_P130_instance_;

const NamedLdrImmediate_Ldrh_Rule_74_A1_P152 LdrImmediate_Ldrh_Rule_74_A1_P152_instance_;

const NamedLdrImmediate_Ldrh_Rule_75_A1_P154 LdrImmediate_Ldrh_Rule_75_A1_P154_instance_;

const NamedLdrImmediate_Ldrsb_Rule_78_A1_P160 LdrImmediate_Ldrsb_Rule_78_A1_P160_instance_;

@@ -276,13 +287,19 @@

const NamedLdrImmediate_ldrsb_Rule_79_A1_162 LdrImmediate_ldrsb_Rule_79_A1_162_instance_;

const NamedLdrImmediateDouble_Ldrd_Rule_66_A1_P136 LdrImmediateDouble_Ldrd_Rule_66_A1_P136_instance_;

const NamedLdrImmediateDouble_Ldrd_Rule_67_A1_P138 LdrImmediateDouble_Ldrd_Rule_67_A1_P138_instance_;

+ const NamedLdrRegister_Ldr_Rule_60_A1_P124 LdrRegister_Ldr_Rule_60_A1_P124_instance_;

+ const NamedLdrRegister_Ldrb_Rule_64_A1_P132 LdrRegister_Ldrb_Rule_64_A1_P132_instance_;

const NamedLdrRegister_Ldrh_Rule_76_A1_P156 LdrRegister_Ldrh_Rule_76_A1_P156_instance_;

const NamedLdrRegister_Ldrsb_Rule_80_A1_P164 LdrRegister_Ldrsb_Rule_80_A1_P164_instance_;

const NamedLdrRegister_Ldrsh_Rule_84_A1_P172 LdrRegister_Ldrsh_Rule_84_A1_P172_instance_;

const NamedLdrRegisterDouble_Ldrd_Rule_68_A1_P140 LdrRegisterDouble_Ldrd_Rule_68_A1_P140_instance_;

const NamedMaskAddress_Bic_Rule_19_A1_P50 MaskAddress_Bic_Rule_19_A1_P50_instance_;

+ const NamedStrImmediate_Str_Rule_194_A1_P384 StrImmediate_Str_Rule_194_A1_P384_instance_;

+ const NamedStrImmediate_Strb_Rule_197_A1_P390 StrImmediate_Strb_Rule_197_A1_P390_instance_;

const NamedStrImmediate_Strh_Rule_207_A1_P410 StrImmediate_Strh_Rule_207_A1_P410_instance_;

const NamedStrImmediateDouble_Strd_Rule_200_A1_P396 StrImmediateDouble_Strd_Rule_200_A1_P396_instance_;

+ const NamedStrRegister_Str_Rule_195_A1_P386 StrRegister_Str_Rule_195_A1_P386_instance_;

+ const NamedStrRegister_Strb_Rule_198_A1_P392 StrRegister_Strb_Rule_198_A1_P392_instance_;

const NamedStrRegister_Strh_Rule_208_A1_P412 StrRegister_Strh_Rule_208_A1_P412_instance_;

const NamedStrRegisterDouble_Strd_Rule_201_A1_P398 StrRegisterDouble_Strd_Rule_201_A1_P398_instance_;

const NamedTestIfAddressMasked_Tst_Rule_230_A1_P454 TestIfAddressMasked_Tst_Rule_230_A1_P454_instance_;

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