Define a baseline and testing patterns for ARM load_store_word_byte table.

src/trusted/validator_arm/gen/arm32_decode_named_decoder.h

 /*
  * Copyright 2012 The Native Client Authors.  All rights reserved.
  * Use of this source code is governed by a BSD-style license that can
  * be found in the LICENSE file.
  */
 
 // DO NOT EDIT: GENERATED CODE
 
 #ifndef NACL_TRUSTED_BUT_NOT_TCB
 #error This file is not meant for use in the TCB
@@ skipping 114 matching lines @@
   const NamedCondNop_Yield_Rule_413_A1_P812 CondNop_Yield_Rule_413_A1_P812_instance_;
   const NamedCoprocessorOp_None CoprocessorOp_None_instance_;
   const NamedDataProc_None DataProc_None_instance_;
   const NamedDeprecated_None Deprecated_None_instance_;
   const NamedEffectiveNoOp_None EffectiveNoOp_None_instance_;
   const NamedForbidden_None Forbidden_None_instance_;
   const NamedForbiddenCondNop_Msr_Rule_B6_1_6_A1_PB6_12 ForbiddenCondNop_Msr_Rule_B6_1_6_A1_PB6_12_instance_;
   const NamedForbiddenCondNop_Sev_Rule_158_A1_P316 ForbiddenCondNop_Sev_Rule_158_A1_P316_instance_;
   const NamedForbiddenCondNop_Wfe_Rule_411_A1_P808 ForbiddenCondNop_Wfe_Rule_411_A1_P808_instance_;
   const NamedForbiddenCondNop_Wfi_Rule_412_A1_P810 ForbiddenCondNop_Wfi_Rule_412_A1_P810_instance_;
-  const NamedLoad2RegisterImmediateDoubleOp_Ldrd_Rule_66_A1_P136 Load2RegisterImmediateDoubleOp_Ldrd_Rule_66_A1_P136_instance_;
-  const NamedLoad2RegisterImmediateDoubleOp_Ldrd_Rule_67_A1_P138 Load2RegisterImmediateDoubleOp_Ldrd_Rule_67_A1_P138_instance_;
-  const NamedLoad2RegisterImmediateOp_Ldrh_Rule_74_A1_P152 Load2RegisterImmediateOp_Ldrh_Rule_74_A1_P152_instance_;
-  const NamedLoad2RegisterImmediateOp_Ldrh_Rule_75_A1_P154 Load2RegisterImmediateOp_Ldrh_Rule_75_A1_P154_instance_;
-  const NamedLoad2RegisterImmediateOp_Ldrsb_Rule_78_A1_P160 Load2RegisterImmediateOp_Ldrsb_Rule_78_A1_P160_instance_;
-  const NamedLoad2RegisterImmediateOp_Ldrsh_Rule_82_A1_P168 Load2RegisterImmediateOp_Ldrsh_Rule_82_A1_P168_instance_;
-  const NamedLoad2RegisterImmediateOp_Ldrsh_Rule_83_A1_P170 Load2RegisterImmediateOp_Ldrsh_Rule_83_A1_P170_instance_;
-  const NamedLoad2RegisterImmediateOp_ldrsb_Rule_79_A1_162 Load2RegisterImmediateOp_ldrsb_Rule_79_A1_162_instance_;
+  const NamedLoad2RegisterImm12Op_Ldr_Rule_58_A1_P120 Load2RegisterImm12Op_Ldr_Rule_58_A1_P120_instance_;
+  const NamedLoad2RegisterImm12Op_Ldr_Rule_59_A1_P122 Load2RegisterImm12Op_Ldr_Rule_59_A1_P122_instance_;
+  const NamedLoad2RegisterImm12Op_Ldrb_Rule_62_A1_P128 Load2RegisterImm12Op_Ldrb_Rule_62_A1_P128_instance_;
+  const NamedLoad2RegisterImm12Op_Ldrb_Rule_63_A1_P130 Load2RegisterImm12Op_Ldrb_Rule_63_A1_P130_instance_;
+  const NamedLoad2RegisterImm8DoubleOp_Ldrd_Rule_66_A1_P136 Load2RegisterImm8DoubleOp_Ldrd_Rule_66_A1_P136_instance_;
+  const NamedLoad2RegisterImm8DoubleOp_Ldrd_Rule_67_A1_P138 Load2RegisterImm8DoubleOp_Ldrd_Rule_67_A1_P138_instance_;
+  const NamedLoad2RegisterImm8Op_Ldrh_Rule_74_A1_P152 Load2RegisterImm8Op_Ldrh_Rule_74_A1_P152_instance_;
+  const NamedLoad2RegisterImm8Op_Ldrh_Rule_75_A1_P154 Load2RegisterImm8Op_Ldrh_Rule_75_A1_P154_instance_;
+  const NamedLoad2RegisterImm8Op_Ldrsb_Rule_78_A1_P160 Load2RegisterImm8Op_Ldrsb_Rule_78_A1_P160_instance_;
+  const NamedLoad2RegisterImm8Op_Ldrsh_Rule_82_A1_P168 Load2RegisterImm8Op_Ldrsh_Rule_82_A1_P168_instance_;
+  const NamedLoad2RegisterImm8Op_Ldrsh_Rule_83_A1_P170 Load2RegisterImm8Op_Ldrsh_Rule_83_A1_P170_instance_;
+  const NamedLoad2RegisterImm8Op_ldrsb_Rule_79_A1_162 Load2RegisterImm8Op_ldrsb_Rule_79_A1_162_instance_;
   const NamedLoad3RegisterDoubleOp_Ldrd_Rule_68_A1_P140 Load3RegisterDoubleOp_Ldrd_Rule_68_A1_P140_instance_;
+  const NamedLoad3RegisterImm5Op_Ldr_Rule_60_A1_P124 Load3RegisterImm5Op_Ldr_Rule_60_A1_P124_instance_;
+  const NamedLoad3RegisterImm5Op_Ldrb_Rule_64_A1_P132 Load3RegisterImm5Op_Ldrb_Rule_64_A1_P132_instance_;
   const NamedLoad3RegisterOp_Ldrh_Rule_76_A1_P156 Load3RegisterOp_Ldrh_Rule_76_A1_P156_instance_;
   const NamedLoad3RegisterOp_Ldrsb_Rule_80_A1_P164 Load3RegisterOp_Ldrsb_Rule_80_A1_P164_instance_;
   const NamedLoad3RegisterOp_Ldrsh_Rule_84_A1_P172 Load3RegisterOp_Ldrsh_Rule_84_A1_P172_instance_;
   const NamedLoadCoprocessor_None LoadCoprocessor_None_instance_;
   const NamedLoadDoubleExclusive_None LoadDoubleExclusive_None_instance_;
   const NamedLoadExclusive_None LoadExclusive_None_instance_;
-  const NamedLoadImmediate_None LoadImmediate_None_instance_;
   const NamedLoadMultiple_None LoadMultiple_None_instance_;
-  const NamedLoadRegister_None LoadRegister_None_instance_;
   const NamedLongMultiply_None LongMultiply_None_instance_;
   const NamedMaskedBinary2RegisterImmediateOp_Bic_Rule_19_A1_P50 MaskedBinary2RegisterImmediateOp_Bic_Rule_19_A1_P50_instance_;
   const NamedMaskedBinaryRegisterImmediateTest_Tst_Rule_230_A1_P454 MaskedBinaryRegisterImmediateTest_Tst_Rule_230_A1_P454_instance_;
   const NamedMoveDoubleFromCoprocessor_None MoveDoubleFromCoprocessor_None_instance_;
   const NamedMoveFromCoprocessor_None MoveFromCoprocessor_None_instance_;
   const NamedMoveToStatusRegister_None MoveToStatusRegister_None_instance_;
   const NamedMultiply_None Multiply_None_instance_;
   const NamedPackSatRev_None PackSatRev_None_instance_;
   const NamedRoadblock_None Roadblock_None_instance_;
   const NamedSatAddSub_None SatAddSub_None_instance_;
-  const NamedStore2RegisterImmediateDoubleOp_Strd_Rule_200_A1_P396 Store2RegisterImmediateDoubleOp_Strd_Rule_200_A1_P396_instance_;
-  const NamedStore2RegisterImmediateOp_Strh_Rule_207_A1_P410 Store2RegisterImmediateOp_Strh_Rule_207_A1_P410_instance_;
+  const NamedStore2RegisterImm12Op_Str_Rule_194_A1_P384 Store2RegisterImm12Op_Str_Rule_194_A1_P384_instance_;
+  const NamedStore2RegisterImm12Op_Strb_Rule_197_A1_P390 Store2RegisterImm12Op_Strb_Rule_197_A1_P390_instance_;
+  const NamedStore2RegisterImm8DoubleOp_Strd_Rule_200_A1_P396 Store2RegisterImm8DoubleOp_Strd_Rule_200_A1_P396_instance_;
+  const NamedStore2RegisterImm8Op_Strh_Rule_207_A1_P410 Store2RegisterImm8Op_Strh_Rule_207_A1_P410_instance_;
   const NamedStore3RegisterDoubleOp_Strd_Rule_201_A1_P398 Store3RegisterDoubleOp_Strd_Rule_201_A1_P398_instance_;
+  const NamedStore3RegisterImm5Op_Str_Rule_195_A1_P386 Store3RegisterImm5Op_Str_Rule_195_A1_P386_instance_;
+  const NamedStore3RegisterImm5Op_Strb_Rule_198_A1_P392 Store3RegisterImm5Op_Strb_Rule_198_A1_P392_instance_;
   const NamedStore3RegisterOp_Strh_Rule_208_A1_P412 Store3RegisterOp_Strh_Rule_208_A1_P412_instance_;
   const NamedStoreCoprocessor_None StoreCoprocessor_None_instance_;
   const NamedStoreExclusive_None StoreExclusive_None_instance_;
   const NamedStoreImmediate_None StoreImmediate_None_instance_;
-  const NamedStoreRegister_None StoreRegister_None_instance_;
   const NamedUnary1RegisterBitRange_Bfc_17_A1_P46 Unary1RegisterBitRange_Bfc_17_A1_P46_instance_;
   const NamedUnary1RegisterImmediateOp_Adr_Rule_10_A1_P32 Unary1RegisterImmediateOp_Adr_Rule_10_A1_P32_instance_;
   const NamedUnary1RegisterImmediateOp_Adr_Rule_10_A2_P32 Unary1RegisterImmediateOp_Adr_Rule_10_A2_P32_instance_;
   const NamedUnary1RegisterImmediateOp_Mov_Rule_96_A1_P194 Unary1RegisterImmediateOp_Mov_Rule_96_A1_P194_instance_;
   const NamedUnary1RegisterImmediateOp_Mov_Rule_96_A2_P_194 Unary1RegisterImmediateOp_Mov_Rule_96_A2_P_194_instance_;
   const NamedUnary1RegisterImmediateOp_Mvn_Rule_106_A1_P214 Unary1RegisterImmediateOp_Mvn_Rule_106_A1_P214_instance_;
   const NamedUnary2RegisterImmedShiftedOp_Asr_Rule_14_A1_P40 Unary2RegisterImmedShiftedOp_Asr_Rule_14_A1_P40_instance_;
   const NamedUnary2RegisterImmedShiftedOp_Lsl_Rule_88_A1_P178 Unary2RegisterImmedShiftedOp_Lsl_Rule_88_A1_P178_instance_;
   const NamedUnary2RegisterImmedShiftedOp_Lsr_Rule_90_A1_P182 Unary2RegisterImmedShiftedOp_Lsr_Rule_90_A1_P182_instance_;
   const NamedUnary2RegisterImmedShiftedOp_Mvn_Rule_107_A1_P216 Unary2RegisterImmedShiftedOp_Mvn_Rule_107_A1_P216_instance_;
@@ skipping 80 matching lines @@
   const NamedDontCareInstRnRsRmNotPc_Cmp_Rule_37_A1_P84 DontCareInstRnRsRmNotPc_Cmp_Rule_37_A1_P84_instance_;
   const NamedDontCareInstRnRsRmNotPc_Teq_Rule_229_A1_P452 DontCareInstRnRsRmNotPc_Teq_Rule_229_A1_P452_instance_;
   const NamedDontCareInstRnRsRmNotPc_Tst_Rule_232_A1_P458 DontCareInstRnRsRmNotPc_Tst_Rule_232_A1_P458_instance_;
   const NamedEffectiveNoOp_Dbg_Rule_40_A1_P88 EffectiveNoOp_Dbg_Rule_40_A1_P88_instance_;
   const NamedEffectiveNoOp_Nop_Rule_110_A1_P222 EffectiveNoOp_Nop_Rule_110_A1_P222_instance_;
   const NamedEffectiveNoOp_Yield_Rule_413_A1_P812 EffectiveNoOp_Yield_Rule_413_A1_P812_instance_;
   const NamedForbidden_Msr_Rule_B6_1_6_A1_PB6_12 Forbidden_Msr_Rule_B6_1_6_A1_PB6_12_instance_;
   const NamedForbidden_Sev_Rule_158_A1_P316 Forbidden_Sev_Rule_158_A1_P316_instance_;
   const NamedForbidden_Wfe_Rule_411_A1_P808 Forbidden_Wfe_Rule_411_A1_P808_instance_;
   const NamedForbidden_Wfi_Rule_412_A1_P810 Forbidden_Wfi_Rule_412_A1_P810_instance_;
+  const NamedLdrImmediate_Ldr_Rule_58_A1_P120 LdrImmediate_Ldr_Rule_58_A1_P120_instance_;
+  const NamedLdrImmediate_Ldr_Rule_59_A1_P122 LdrImmediate_Ldr_Rule_59_A1_P122_instance_;
+  const NamedLdrImmediate_Ldrb_Rule_62_A1_P128 LdrImmediate_Ldrb_Rule_62_A1_P128_instance_;
+  const NamedLdrImmediate_Ldrb_Rule_63_A1_P130 LdrImmediate_Ldrb_Rule_63_A1_P130_instance_;
   const NamedLdrImmediate_Ldrh_Rule_74_A1_P152 LdrImmediate_Ldrh_Rule_74_A1_P152_instance_;
   const NamedLdrImmediate_Ldrh_Rule_75_A1_P154 LdrImmediate_Ldrh_Rule_75_A1_P154_instance_;
   const NamedLdrImmediate_Ldrsb_Rule_78_A1_P160 LdrImmediate_Ldrsb_Rule_78_A1_P160_instance_;
   const NamedLdrImmediate_Ldrsh_Rule_82_A1_P168 LdrImmediate_Ldrsh_Rule_82_A1_P168_instance_;
   const NamedLdrImmediate_Ldrsh_Rule_83_A1_P170 LdrImmediate_Ldrsh_Rule_83_A1_P170_instance_;
   const NamedLdrImmediate_ldrsb_Rule_79_A1_162 LdrImmediate_ldrsb_Rule_79_A1_162_instance_;
   const NamedLdrImmediateDouble_Ldrd_Rule_66_A1_P136 LdrImmediateDouble_Ldrd_Rule_66_A1_P136_instance_;
   const NamedLdrImmediateDouble_Ldrd_Rule_67_A1_P138 LdrImmediateDouble_Ldrd_Rule_67_A1_P138_instance_;
+  const NamedLdrRegister_Ldr_Rule_60_A1_P124 LdrRegister_Ldr_Rule_60_A1_P124_instance_;
+  const NamedLdrRegister_Ldrb_Rule_64_A1_P132 LdrRegister_Ldrb_Rule_64_A1_P132_instance_;
   const NamedLdrRegister_Ldrh_Rule_76_A1_P156 LdrRegister_Ldrh_Rule_76_A1_P156_instance_;
   const NamedLdrRegister_Ldrsb_Rule_80_A1_P164 LdrRegister_Ldrsb_Rule_80_A1_P164_instance_;
   const NamedLdrRegister_Ldrsh_Rule_84_A1_P172 LdrRegister_Ldrsh_Rule_84_A1_P172_instance_;
   const NamedLdrRegisterDouble_Ldrd_Rule_68_A1_P140 LdrRegisterDouble_Ldrd_Rule_68_A1_P140_instance_;
   const NamedMaskAddress_Bic_Rule_19_A1_P50 MaskAddress_Bic_Rule_19_A1_P50_instance_;
+  const NamedStrImmediate_Str_Rule_194_A1_P384 StrImmediate_Str_Rule_194_A1_P384_instance_;
+  const NamedStrImmediate_Strb_Rule_197_A1_P390 StrImmediate_Strb_Rule_197_A1_P390_instance_;
   const NamedStrImmediate_Strh_Rule_207_A1_P410 StrImmediate_Strh_Rule_207_A1_P410_instance_;
   const NamedStrImmediateDouble_Strd_Rule_200_A1_P396 StrImmediateDouble_Strd_Rule_200_A1_P396_instance_;
+  const NamedStrRegister_Str_Rule_195_A1_P386 StrRegister_Str_Rule_195_A1_P386_instance_;
+  const NamedStrRegister_Strb_Rule_198_A1_P392 StrRegister_Strb_Rule_198_A1_P392_instance_;
   const NamedStrRegister_Strh_Rule_208_A1_P412 StrRegister_Strh_Rule_208_A1_P412_instance_;
   const NamedStrRegisterDouble_Strd_Rule_201_A1_P398 StrRegisterDouble_Strd_Rule_201_A1_P398_instance_;
   const NamedTestIfAddressMasked_Tst_Rule_230_A1_P454 TestIfAddressMasked_Tst_Rule_230_A1_P454_instance_;
  private:
 
   // The following list of methods correspond to each decoder table,
   // and implements the pattern matching of the corresponding bit
   // patterns. After matching the corresponding bit patterns, they
   // either call other methods in this list (corresponding to another
   // decoder table), or they return the instance field that implements
@@ skipping 60 matching lines @@
   inline const NamedClassDecoder& decode_super_cop(
       const nacl_arm_dec::Instruction insn) const;
   inline const NamedClassDecoder& decode_sync(
       const nacl_arm_dec::Instruction insn) const;
   inline const NamedClassDecoder& decode_unconditional(
       const nacl_arm_dec::Instruction insn) const;
 };
 
 } // namespace nacl_arm_test
 #endif  // NATIVE_CLIENT_SRC_TRUSTED_VALIDATOR_ARM_GEN_ARM32_DECODE_NAMED_DECODER_H_