| Index: src/trusted/validator_arm/gen/arm32_decode.cc
|
| ===================================================================
|
| --- src/trusted/validator_arm/gen/arm32_decode.cc (revision 8506)
|
| +++ src/trusted/validator_arm/gen/arm32_decode.cc (working copy)
|
| @@ -17,6 +17,7 @@
|
| Arm32DecoderState::Arm32DecoderState() : DecoderState()
|
| , Binary2RegisterImmedShiftedTest_instance_()
|
| , Binary3RegisterImmedShiftedOp_instance_()
|
| + , Binary3RegisterImmedShiftedOpRnNotSp_instance_()
|
| , Binary3RegisterOp_instance_()
|
| , Binary3RegisterShiftedTest_instance_()
|
| , Binary4RegisterShiftedOp_instance_()
|
| @@ -250,6 +251,22 @@
|
| const Instruction insn) const
|
| {
|
| UNREFERENCED_PARAMETER(insn);
|
| + if (((insn & 0x01E00000) == 0x00400000) && (true) && (true))
|
| +
|
| + return Binary3RegisterImmedShiftedOpRnNotSp_instance_;
|
| +
|
| + if (((insn & 0x01E00000) == 0x00800000) && (true) && (true))
|
| +
|
| + return Binary3RegisterImmedShiftedOpRnNotSp_instance_;
|
| +
|
| + if (((insn & 0x01E00000) == 0x00A00000) && (true) && (true))
|
| +
|
| + return Binary3RegisterImmedShiftedOp_instance_;
|
| +
|
| + if (((insn & 0x01E00000) == 0x01800000) && (true) && (true))
|
| +
|
| + return Binary3RegisterImmedShiftedOp_instance_;
|
| +
|
| if (((insn & 0x01E00000) == 0x01A00000) && ((insn & 0x00000F80) != 0x00000000) && ((insn & 0x00000060) == 0x00000000))
|
|
|
| return Unary2RegisterImmedShiftedOp_instance_;
|
| @@ -278,16 +295,20 @@
|
|
|
| return Unary2RegisterImmedShiftedOp_instance_;
|
|
|
| - if (((insn & 0x01900000) == 0x01100000) && (true) && (true))
|
| + if (((insn & 0x00E00000) == 0x00C00000) && (true) && (true))
|
|
|
| - return Binary2RegisterImmedShiftedTest_instance_;
|
| + return Binary3RegisterImmedShiftedOp_instance_;
|
|
|
| - if (((insn & 0x01A00000) == 0x01800000) && (true) && (true))
|
| + if (((insn & 0x01600000) == 0x00600000) && (true) && (true))
|
|
|
| return Binary3RegisterImmedShiftedOp_instance_;
|
|
|
| - if (((insn & 0x01000000) == 0x00000000) && (true) && (true))
|
| + if (((insn & 0x01900000) == 0x01100000) && (true) && (true))
|
|
|
| + return Binary2RegisterImmedShiftedTest_instance_;
|
| +
|
| + if (((insn & 0x01C00000) == 0x00000000) && (true) && (true))
|
| +
|
| return Binary3RegisterImmedShiftedOp_instance_;
|
|
|
| // Catch any attempt to fall though ...
|
|
|