Clean up testing of instructions. Allow testing to quit if test pattern tests

src/trusted/validator_arm/gen/arm32_decode.cc

 /*
  * Copyright 2012 The Native Client Authors.  All rights reserved.
  * Use of this source code is governed by a BSD-style license that can
  * be found in the LICENSE file.
  */
 
 // DO NOT EDIT: GENERATED CODE
 
 
 #include "native_client/src/trusted/validator_arm/gen/arm32_decode.h"
 
 #include <stdio.h>
 
 namespace nacl_arm_dec {
 
 
 Arm32DecoderState::Arm32DecoderState() : DecoderState()
   , Binary2RegisterImmedShiftedTest_instance_()
   , Binary3RegisterImmedShiftedOp_instance_()
+  , Binary3RegisterImmedShiftedOpRnNotSp_instance_()
   , Binary3RegisterOp_instance_()
   , Binary3RegisterShiftedTest_instance_()
   , Binary4RegisterShiftedOp_instance_()
   , Branch_instance_()
   , Breakpoint_instance_()
   , BxBlx_instance_()
   , CoprocessorOp_instance_()
   , DataProc_instance_()
   , Defs12To15RdRnRsRmNotPc_instance_()
   , Deprecated_instance_()
@@ skipping 213 matching lines @@
           insn.bits(31, 0));
   return Forbidden_instance_;
 }
 
 // Implementation of table: dp_reg.
 // Specified by: See Section A5.2.1
 const ClassDecoder& Arm32DecoderState::decode_dp_reg(
      const Instruction insn) const
 {
   UNREFERENCED_PARAMETER(insn);
+  if (((insn & 0x01E00000) == 0x00400000) && (true) && (true))
+
+    return Binary3RegisterImmedShiftedOpRnNotSp_instance_;
+
+  if (((insn & 0x01E00000) == 0x00800000) && (true) && (true))
+
+    return Binary3RegisterImmedShiftedOpRnNotSp_instance_;
+
+  if (((insn & 0x01E00000) == 0x00A00000) && (true) && (true))
+
+    return Binary3RegisterImmedShiftedOp_instance_;
+
+  if (((insn & 0x01E00000) == 0x01800000) && (true) && (true))
+
+    return Binary3RegisterImmedShiftedOp_instance_;
+
   if (((insn & 0x01E00000) == 0x01A00000) && ((insn & 0x00000F80) != 0x00000000) && ((insn & 0x00000060) == 0x00000000))
 
     return Unary2RegisterImmedShiftedOp_instance_;
 
   if (((insn & 0x01E00000) == 0x01A00000) && ((insn & 0x00000F80) != 0x00000000) && ((insn & 0x00000060) == 0x00000060))
 
     return Unary2RegisterImmedShiftedOp_instance_;
 
   if (((insn & 0x01E00000) == 0x01A00000) && ((insn & 0x00000F80) == 0x00000000) && ((insn & 0x00000060) == 0x00000000))
 
     return Unary2RegisterOp_instance_;
 
   if (((insn & 0x01E00000) == 0x01A00000) && ((insn & 0x00000F80) == 0x00000000) && ((insn & 0x00000060) == 0x00000060))
 
     return Unary2RegisterOp_instance_;
 
   if (((insn & 0x01E00000) == 0x01A00000) && (true) && ((insn & 0x00000060) == 0x00000020))
 
     return Unary2RegisterImmedShiftedOp_instance_;
 
   if (((insn & 0x01E00000) == 0x01A00000) && (true) && ((insn & 0x00000060) == 0x00000040))
 
     return Unary2RegisterImmedShiftedOp_instance_;
 
   if (((insn & 0x01E00000) == 0x01E00000) && (true) && (true))
 
     return Unary2RegisterImmedShiftedOp_instance_;
 
+  if (((insn & 0x00E00000) == 0x00C00000) && (true) && (true))
+
+    return Binary3RegisterImmedShiftedOp_instance_;
+
+  if (((insn & 0x01600000) == 0x00600000) && (true) && (true))
+
+    return Binary3RegisterImmedShiftedOp_instance_;
+
   if (((insn & 0x01900000) == 0x01100000) && (true) && (true))
 
     return Binary2RegisterImmedShiftedTest_instance_;
 
-  if (((insn & 0x01A00000) == 0x01800000) && (true) && (true))
-
-    return Binary3RegisterImmedShiftedOp_instance_;
-
-  if (((insn & 0x01000000) == 0x00000000) && (true) && (true))
+  if (((insn & 0x01C00000) == 0x00000000) && (true) && (true))
 
     return Binary3RegisterImmedShiftedOp_instance_;
 
   // Catch any attempt to fall though ...
   fprintf(stderr, "TABLE IS INCOMPLETE: dp_reg could not parse %08X",
           insn.bits(31, 0));
   return Forbidden_instance_;
 }
 
 // Implementation of table: dp_reg_shifted.
@@ skipping 1230 matching lines @@
   fprintf(stderr, "TABLE IS INCOMPLETE: unconditional could not parse %08X",
           insn.bits(31, 0));
   return Forbidden_instance_;
 }
 
 const ClassDecoder& Arm32DecoderState::decode(const Instruction insn) const {
   return decode_ARMv7(insn);
 }
 
 }  // namespace nacl_arm_dec