Finish separation of testing from sel_ldr validation. Also, automate

src/trusted/validator_arm/inst_classes.cc

Index: src/trusted/validator_arm/inst_classes.cc
===================================================================
--- src/trusted/validator_arm/inst_classes.cc	(revision 8201)
+++ src/trusted/validator_arm/inst_classes.cc	(working copy)
@@ -6,19 +6,12 @@
 
 #include "native_client/src/trusted/validator_arm/inst_classes.h"
 
-#include <assert.h>
 #include <string.h>
 
 // Implementations of instruction classes, for those not completely defined in
 
 namespace nacl_arm_dec {
 
-const char* ClassDecoder::name() const {
-  // This should never be called!
-  assert(0);
-  return "???";
-}
-
 // A utility function: given a modified-immediate-form instruction, extracts
 // the immediate value.  This is used to analyze BIC and TST.
 //
@@ -45,6 +38,7 @@
   // Unsafe if any register contains PC (ARM restriction).
   if ((d_.reg(i) + n_.reg(i) + s_.reg(i) + m_.reg(i))[kRegisterPc])
     return UNPREDICTABLE;
+
   // Note: We would restrict out PC as well for Rd in NaCl, but no need
   // since the ARM restriction doesn't allow it anyway.
   return MAY_BE_SAFE;
@@ -58,6 +52,7 @@
 SafetyLevel Unary3RegisterShiftedOp::safety(Instruction i) const {
   // Unsafe if any register contains PC (ARM restriction).
   if ((d_.reg(i) + s_.reg(i) + m_.reg(i))[kRegisterPc]) return UNPREDICTABLE;
+
   // Note: We would restrict out PC as well for Rd in NaCl, but no need
   // since the ARM restriction doesn't allow it anyway.
   return MAY_BE_SAFE;