Finish separation of testing from sel_ldr validation. Also, automate

src/trusted/validator_arm/inst_classes.cc

 /*
  * Copyright (c) 2012 The Native Client Authors. All rights reserved.
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 #include "native_client/src/trusted/validator_arm/inst_classes.h"
 
-#include <assert.h>
 #include <string.h>
 
 // Implementations of instruction classes, for those not completely defined in
 
 namespace nacl_arm_dec {
 
-const char* ClassDecoder::name() const {
-  // This should never be called!
-  assert(0);
-  return "???";
-}
-
 // A utility function: given a modified-immediate-form instruction, extracts
 // the immediate value.  This is used to analyze BIC and TST.
 //
 // This encoding is described in Section A5.2.4.
 static uint32_t get_modified_immediate(Instruction i) {
   int rotation = i.bits(11, 8) * 2;
   uint32_t value = i.bits(7, 0);
 
   if (rotation == 0) return value;
 
   return (value >> rotation) | (value << (32 - rotation));
 }
 
 // Breakpoint
 
 bool Breakpoint::is_literal_pool_head(const Instruction i) const {
   return i.condition() == Instruction::AL
       && i.bits(19, 8) == 0x777
       && i.bits(3, 0) == 0x7;
 }
 
 // Binary4RegisterShiftedOp
 SafetyLevel Binary4RegisterShiftedOp::safety(Instruction i) const {
   // Unsafe if any register contains PC (ARM restriction).
   if ((d_.reg(i) + n_.reg(i) + s_.reg(i) + m_.reg(i))[kRegisterPc])
     return UNPREDICTABLE;
+
   // Note: We would restrict out PC as well for Rd in NaCl, but no need
   // since the ARM restriction doesn't allow it anyway.
   return MAY_BE_SAFE;
 }
 
 RegisterList Binary4RegisterShiftedOp::defs(const Instruction i) const {
   return d_.reg(i) + flags_.reg_if_updated(i);
 }
 
 // Unary3RegisterShiftedOp
 SafetyLevel Unary3RegisterShiftedOp::safety(Instruction i) const {
   // Unsafe if any register contains PC (ARM restriction).
   if ((d_.reg(i) + s_.reg(i) + m_.reg(i))[kRegisterPc]) return UNPREDICTABLE;
+
   // Note: We would restrict out PC as well for Rd in NaCl, but no need
   // since the ARM restriction doesn't allow it anyway.
   return MAY_BE_SAFE;
 }
 
 RegisterList Unary3RegisterShiftedOp::defs(const Instruction i) const {
   return d_.reg(i) + flags_.reg_if_updated(i);
 }
 
 // Data processing and arithmetic
@@ skipping 417 matching lines @@
   return kRegisterPc + (PreindexingFlag(i) ? kRegisterLink : kRegisterNone);
 }
 
 int32_t Branch::branch_target_offset(const Instruction i) const {
   // Sign extend and shift left 2:
   int32_t offset = (int32_t)(i.bits(23, 0) << 8) >> 6;
   return offset + 8;  // because r15 reads as 8 bytes ahead
 }
 
 }  // namespace