Finish separation of testing from sel_ldr validation. Also, automate

src/trusted/validator_arm/armv7.table

Index: src/trusted/validator_arm/armv7.table
===================================================================
--- src/trusted/validator_arm/armv7.table	(revision 8201)
+++ src/trusted/validator_arm/armv7.table	(working copy)
@@ -25,6 +25,41 @@
 # If an encoding is not valid in every ARM architecture rev, the instruction
 # class may indicate the rev or feature that makes the encoding valid in
 # parentheses.
+#
+# For documentation and testing, an "=InstClass" can be followed by up to 3

[robertm, 2012/04/11 01:28:43]

thanks for reverse engineering and documenting it

[Karl, 2012/04/16 23:18:10]

Done.

+# additional identifiers, and has the form:
+#     =InstClass Rule Pattern Constraints
+# where
+#     InstClass - is the class decoder to return when matched.
+#     Rule - is the Arm rule that applies to the match (see below).
+#     Pattern - is a bitpattern for testing instances of the rule.
+#     Constraints - identifies what additional constraints are assumed
+#            by the corresponding rule.
+#
+# The Rules are identified with an identifier of the form:
+#     NNN_Rule_SS_AA_Pppp
+# where
+#    NNN is the nmenonic of the instruction.
+#    SS is the section number in A8.6.SS that define the instruction.
+#    AA is the instruction form on that page,
+#    pp is the page number in A8-pp that the instruction is on.
+#
+# Patterns are sequences of 32 characters as follows:
+#   '1' - Bit must be value 1.
+#   '0' - Bit must be value 0.
+#   'aaa...aa' (for some sequence of m lower case letters) -
+#       Try all possible combinations of bits for the m bytes.
+#   'AAA...A'  (for some sequence of m upper case letters) -
+#       Try the following combinations:
+#         (1) All m bits set to 1.
+#         (2) All m bits set to 0.
+#         (3) For each 4-bit subsequence, try all combinations,
+#             setting remaining bits to 1.
+#         (4) For each 4-bit subsequence, try all combinations,
+#             setting remaining bits to 0.
+#
+# Constraints identifiers used are:
+#    RegsNotPc - All register defined by instruction are not Pc (R15).
 
 -- ARMv7 (See Section A5.1)
 cond(31:28) op1(27:25) op(4)
@@ -83,7 +118,9 @@
 0001x      -        =Binary4RegisterShiftedOp    # EOR(register-shifted) A1 A8-98
 0010x      -        =Binary4RegisterShiftedOp    # SUB(register-shifted) A1 A8-424
 0011x      -        =Binary4RegisterShiftedOp    # RSB(register-shifted) A1 A8-288
-0100x      -        =Binary4RegisterShiftedOp    # ADD(register-shifted) A1 A8-26
+0100x      -        =Binary4RegisterShiftedOp      Add_Rule_7_A1_P26 \
+                                                   cccc0000100snnnnddddssss0tt1mmmm \
+                                                   RegsNotPc
 0101x      -        =Binary4RegisterShiftedOp    # ADC(register-shifted) A1 A8-18
 0110x      -        =Binary4RegisterShiftedOp    # SBC(register-shifted) A1 A8-306
 0111x      -        =Binary4RegisterShiftedOp    # RSC(register-shifted) A1 A8-294