Finish separation of testing from sel_ldr validation. Also, automate

src/trusted/validator_arm/armv7.table

 # ARMv7 Instruction Encodings
 #
 # This table is derived from the "ARM Architecture Reference Manual, ARMv7-A
 # and ARMv7-R edition" and is used here with the permission of ARM Limited.
 # Reproduction for purposes other than the development and distribution of
 # Native Client may require the explicit permission of ARM Limited.
 
 # This file defines the Native Client "instruction classes" assigned to every
 # possible ARMv7 instruction encoding.  It is organized into a series of tables,
 # and directly parallels the ARM Architecture Reference Manual cited above.
 #
 # Each table consists of
 # - A name,
 # - A citation in the Architecture Reference Manual,
 # - One or more columns defining bitfields to match, and
 # - One or more rows describing patterns in those bitfields.
 #
 # A leading tilde (~) negates a pattern.  A hyphen (-) is short for a string of
 # don't-care bits (x).  A double-quote (") indicates that a pattern is the same
 # as the row above it.
 #
 # Each row may specify a terminal instruction class ("=InstClass"), or forward
 # the reader to a different table ("->table_name").
 #
 # If an encoding is not valid in every ARM architecture rev, the instruction
 # class may indicate the rev or feature that makes the encoding valid in
 # parentheses.
+#
+# For documentation and testing, an "=InstClass" can be followed by up to 3

[robertm, 2012/04/11 01:28:43]

thanks for reverse engineering and documenting it

[Karl, 2012/04/16 23:18:10]

Done.

+# additional identifiers, and has the form:
+#     =InstClass Rule Pattern Constraints
+# where
+#     InstClass - is the class decoder to return when matched.
+#     Rule - is the Arm rule that applies to the match (see below).
+#     Pattern - is a bitpattern for testing instances of the rule.
+#     Constraints - identifies what additional constraints are assumed
+#            by the corresponding rule.
+#
+# The Rules are identified with an identifier of the form:
+#     NNN_Rule_SS_AA_Pppp
+# where
+#    NNN is the nmenonic of the instruction.
+#    SS is the section number in A8.6.SS that define the instruction.
+#    AA is the instruction form on that page,
+#    pp is the page number in A8-pp that the instruction is on.
+#
+# Patterns are sequences of 32 characters as follows:
+#   '1' - Bit must be value 1.
+#   '0' - Bit must be value 0.
+#   'aaa...aa' (for some sequence of m lower case letters) -
+#       Try all possible combinations of bits for the m bytes.
+#   'AAA...A'  (for some sequence of m upper case letters) -
+#       Try the following combinations:
+#         (1) All m bits set to 1.
+#         (2) All m bits set to 0.
+#         (3) For each 4-bit subsequence, try all combinations,
+#             setting remaining bits to 1.
+#         (4) For each 4-bit subsequence, try all combinations,
+#             setting remaining bits to 0.
+#
+# Constraints identifiers used are:
+#    RegsNotPc - All register defined by instruction are not Pc (R15).
 
 -- ARMv7 (See Section A5.1)
 cond(31:28) op1(27:25) op(4)
 ~1111       00x        -     ->dp_misc
 "           010        -     ->load_store_word_byte
 "           011        0     ->load_store_word_byte
 "           "          1     ->media
 "           10x        -     ->branch_block_xfer
 "           11x        -     ->super_cop
 1111        -          -     ->unconditional
@@ skipping 38 matching lines @@
 "          ~00000    11       =DataProc  # ROR(immediate) A8-278
 1110x      -         -        =DataProc  # BIC(register) A8-52
 1111x      -         -        =DataProc  # MVN(register) A8-216
 
 -- dp_reg_shifted (See Section A5.2.2)
 op1(24:20) op2(6:5)
 0000x      -        =Binary4RegisterShiftedOp    # AND(register-shifted) A1 A8-38
 0001x      -        =Binary4RegisterShiftedOp    # EOR(register-shifted) A1 A8-98
 0010x      -        =Binary4RegisterShiftedOp    # SUB(register-shifted) A1 A8-424
 0011x      -        =Binary4RegisterShiftedOp    # RSB(register-shifted) A1 A8-288
-0100x      -        =Binary4RegisterShiftedOp    # ADD(register-shifted) A1 A8-26
+0100x      -        =Binary4RegisterShiftedOp      Add_Rule_7_A1_P26 \
+                                                   cccc0000100snnnnddddssss0tt1mmmm \
+                                                   RegsNotPc
 0101x      -        =Binary4RegisterShiftedOp    # ADC(register-shifted) A1 A8-18
 0110x      -        =Binary4RegisterShiftedOp    # SBC(register-shifted) A1 A8-306
 0111x      -        =Binary4RegisterShiftedOp    # RSC(register-shifted) A1 A8-294
 10001      -        =Binary3RegisterShiftedTest  # TST(register-shifted) A1 A8-458
 10011      -        =Binary3RegisterShiftedTest  # TEQ(register-shifted) A1 A8-452
 10101      -        =Binary3RegisterShiftedTest  # CMP(register-shifted) A1 A8-84
 10111      -        =Binary3RegisterShiftedTest  # CMN(register-shifted) A1 A8-78
 1100x      -        =Binary4RegisterShiftedOp    # ORR(register-shifted) A1 A8-232
 1101x      00       =DataProc  # LSL(register) A8-180
 "          01       =DataProc  # LSR(register) A8-184
@@ skipping 506 matching lines @@
 "     0x01    =VectorLoad  # VLD2(single)
 "     1001    "
 "     1101    =VectorLoad  # VLD2(single, all lanes)
 "     0x10    =VectorLoad  # VLD3(single)
 "     1010    "
 "     1110    =VectorLoad  # VLD3(single, all lanes)
 "     0x11    =VectorLoad  # VLD4(single)
 "     1011    "
 "     1111    =VectorLoad  # VLD4(single, all lanes)
 -     -       =Undefined   # Note on page A7-27