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1 // Copyright (c) 1994-2006 Sun Microsystems Inc. | 1 // Copyright (c) 1994-2006 Sun Microsystems Inc. |
2 // All Rights Reserved. | 2 // All Rights Reserved. |
3 // | 3 // |
4 // Redistribution and use in source and binary forms, with or without | 4 // Redistribution and use in source and binary forms, with or without |
5 // modification, are permitted provided that the following conditions | 5 // modification, are permitted provided that the following conditions |
6 // are met: | 6 // are met: |
7 // | 7 // |
8 // - Redistributions of source code must retain the above copyright notice, | 8 // - Redistributions of source code must retain the above copyright notice, |
9 // this list of conditions and the following disclaimer. | 9 // this list of conditions and the following disclaimer. |
10 // | 10 // |
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1086 if (fits_shifter(~imm32, rotate_imm, immed_8, NULL)) { | 1086 if (fits_shifter(~imm32, rotate_imm, immed_8, NULL)) { |
1087 *instr ^= kAndBicFlip; | 1087 *instr ^= kAndBicFlip; |
1088 return true; | 1088 return true; |
1089 } | 1089 } |
1090 } | 1090 } |
1091 } | 1091 } |
1092 } | 1092 } |
1093 return false; | 1093 return false; |
1094 } | 1094 } |
1095 | 1095 |
1096 namespace { | |
1097 | 1096 |
1098 // We have to use the temporary register for things that can be relocated even | 1097 // We have to use the temporary register for things that can be relocated even |
1099 // if they can be encoded in the ARM's 12 bits of immediate-offset instruction | 1098 // if they can be encoded in the ARM's 12 bits of immediate-offset instruction |
1100 // space. There is no guarantee that the relocated location can be similarly | 1099 // space. There is no guarantee that the relocated location can be similarly |
1101 // encoded. | 1100 // encoded. |
1102 bool must_output_reloc_info(RelocInfo::Mode rmode, const Assembler* assembler) { | 1101 bool Operand::must_output_reloc_info(const Assembler* assembler) const { |
1103 if (rmode == RelocInfo::EXTERNAL_REFERENCE) { | 1102 if (rmode_ == RelocInfo::EXTERNAL_REFERENCE) { |
1104 if (assembler != NULL && assembler->predictable_code_size()) return true; | 1103 if (assembler != NULL && assembler->predictable_code_size()) return true; |
1105 return assembler->serializer_enabled(); | 1104 return assembler->serializer_enabled(); |
1106 } else if (RelocInfo::IsNone(rmode)) { | 1105 } else if (RelocInfo::IsNone(rmode_)) { |
1107 return false; | 1106 return false; |
1108 } | 1107 } |
1109 return true; | 1108 return true; |
1110 } | 1109 } |
1111 | 1110 |
1112 bool use_mov_immediate_load(const Operand& x, const Assembler* assembler) { | 1111 |
| 1112 static bool use_mov_immediate_load(const Operand& x, |
| 1113 const Assembler* assembler) { |
1113 DCHECK(assembler != nullptr); | 1114 DCHECK(assembler != nullptr); |
1114 if (x.must_output_reloc_info(assembler)) { | 1115 if (x.must_output_reloc_info(assembler)) { |
1115 // Prefer constant pool if data is likely to be patched. | 1116 // Prefer constant pool if data is likely to be patched. |
1116 return false; | 1117 return false; |
1117 } else { | 1118 } else { |
1118 // Otherwise, use immediate load if movw / movt is available. | 1119 // Otherwise, use immediate load if movw / movt is available. |
1119 return CpuFeatures::IsSupported(ARMv7); | 1120 return CpuFeatures::IsSupported(ARMv7); |
1120 } | 1121 } |
1121 } | 1122 } |
1122 | 1123 |
1123 } // namespace | |
1124 | |
1125 bool Operand::must_output_reloc_info(const Assembler* assembler) const { | |
1126 return v8::internal::must_output_reloc_info(rmode_, assembler); | |
1127 } | |
1128 | 1124 |
1129 int Operand::instructions_required(const Assembler* assembler, | 1125 int Operand::instructions_required(const Assembler* assembler, |
1130 Instr instr) const { | 1126 Instr instr) const { |
1131 DCHECK(assembler != nullptr); | 1127 DCHECK(assembler != nullptr); |
1132 if (rm_.is_valid()) return 1; | 1128 if (rm_.is_valid()) return 1; |
1133 uint32_t dummy1, dummy2; | 1129 uint32_t dummy1, dummy2; |
1134 if (must_output_reloc_info(assembler) || | 1130 if (must_output_reloc_info(assembler) || |
1135 !fits_shifter(imm32_, &dummy1, &dummy2, &instr)) { | 1131 !fits_shifter(imm32_, &dummy1, &dummy2, &instr)) { |
1136 // The immediate operand cannot be encoded as a shifter operand, or use of | 1132 // The immediate operand cannot be encoded as a shifter operand, or use of |
1137 // constant pool is required. First account for the instructions required | 1133 // constant pool is required. First account for the instructions required |
1138 // for the constant pool or immediate load | 1134 // for the constant pool or immediate load |
1139 int instructions; | 1135 int instructions; |
1140 if (use_mov_immediate_load(*this, assembler)) { | 1136 if (use_mov_immediate_load(*this, assembler)) { |
1141 DCHECK(CpuFeatures::IsSupported(ARMv7)); | 1137 // A movw / movt or mov / orr immediate load. |
1142 // A movw / movt immediate load. | 1138 instructions = CpuFeatures::IsSupported(ARMv7) ? 2 : 4; |
1143 instructions = 2; | |
1144 } else { | 1139 } else { |
1145 // A small constant pool load. | 1140 // A small constant pool load. |
1146 instructions = 1; | 1141 instructions = 1; |
1147 } | 1142 } |
1148 if ((instr & ~kCondMask) != 13 * B21) { // mov, S not set | 1143 if ((instr & ~kCondMask) != 13 * B21) { // mov, S not set |
1149 // For a mov or mvn instruction which doesn't set the condition | 1144 // For a mov or mvn instruction which doesn't set the condition |
1150 // code, the constant pool or immediate load is enough, otherwise we need | 1145 // code, the constant pool or immediate load is enough, otherwise we need |
1151 // to account for the actual instruction being requested. | 1146 // to account for the actual instruction being requested. |
1152 instructions += 1; | 1147 instructions += 1; |
1153 } | 1148 } |
1154 return instructions; | 1149 return instructions; |
1155 } else { | 1150 } else { |
1156 // No use of constant pool and the immediate operand can be encoded as a | 1151 // No use of constant pool and the immediate operand can be encoded as a |
1157 // shifter operand. | 1152 // shifter operand. |
1158 return 1; | 1153 return 1; |
1159 } | 1154 } |
1160 } | 1155 } |
1161 | 1156 |
1162 | 1157 |
1163 void Assembler::move_32_bit_immediate(Register rd, | 1158 void Assembler::move_32_bit_immediate(Register rd, |
1164 const Operand& x, | 1159 const Operand& x, |
1165 Condition cond) { | 1160 Condition cond) { |
| 1161 uint32_t imm32 = static_cast<uint32_t>(x.imm32_); |
| 1162 if (x.must_output_reloc_info(this)) { |
| 1163 RecordRelocInfo(x.rmode_); |
| 1164 } |
| 1165 |
1166 if (use_mov_immediate_load(x, this)) { | 1166 if (use_mov_immediate_load(x, this)) { |
1167 // use_mov_immediate_load should return false when we need to output | 1167 // use_mov_immediate_load should return false when we need to output |
1168 // relocation info, since we prefer the constant pool for values that | 1168 // relocation info, since we prefer the constant pool for values that |
1169 // can be patched. | 1169 // can be patched. |
1170 DCHECK(!x.must_output_reloc_info(this)); | 1170 DCHECK(!x.must_output_reloc_info(this)); |
1171 Register target = rd.code() == pc.code() ? ip : rd; | 1171 Register target = rd.code() == pc.code() ? ip : rd; |
1172 if (CpuFeatures::IsSupported(ARMv7)) { | 1172 if (CpuFeatures::IsSupported(ARMv7)) { |
1173 uint32_t imm32 = static_cast<uint32_t>(x.imm32_); | |
1174 CpuFeatureScope scope(this, ARMv7); | 1173 CpuFeatureScope scope(this, ARMv7); |
1175 movw(target, imm32 & 0xffff, cond); | 1174 movw(target, imm32 & 0xffff, cond); |
1176 movt(target, imm32 >> 16, cond); | 1175 movt(target, imm32 >> 16, cond); |
1177 } | 1176 } |
1178 if (target.code() != rd.code()) { | 1177 if (target.code() != rd.code()) { |
1179 mov(rd, target, LeaveCC, cond); | 1178 mov(rd, target, LeaveCC, cond); |
1180 } | 1179 } |
1181 } else { | 1180 } else { |
1182 ConstantPoolAddEntry(pc_offset(), x.rmode_, x.imm32_); | 1181 ConstantPoolEntry::Access access = |
| 1182 ConstantPoolAddEntry(pc_offset(), x.rmode_, x.imm32_); |
| 1183 DCHECK(access == ConstantPoolEntry::REGULAR); |
| 1184 USE(access); |
1183 ldr(rd, MemOperand(pc, 0), cond); | 1185 ldr(rd, MemOperand(pc, 0), cond); |
1184 } | 1186 } |
1185 } | 1187 } |
1186 | 1188 |
1187 | 1189 |
1188 void Assembler::addrmod1(Instr instr, | 1190 void Assembler::addrmod1(Instr instr, |
1189 Register rn, | 1191 Register rn, |
1190 Register rd, | 1192 Register rd, |
1191 const Operand& x) { | 1193 const Operand& x) { |
1192 CheckBuffer(); | 1194 CheckBuffer(); |
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2716 // need to add/subtract without losing precision, which requires a | 2718 // need to add/subtract without losing precision, which requires a |
2717 // cookie value that Lithium is probably better positioned to | 2719 // cookie value that Lithium is probably better positioned to |
2718 // choose. | 2720 // choose. |
2719 // We could also add a few peepholes here like detecting 0.0 and | 2721 // We could also add a few peepholes here like detecting 0.0 and |
2720 // -0.0 and doing a vmov from the sequestered d14, forcing denorms | 2722 // -0.0 and doing a vmov from the sequestered d14, forcing denorms |
2721 // to zero (we set flush-to-zero), and normalizing NaN values. | 2723 // to zero (we set flush-to-zero), and normalizing NaN values. |
2722 // We could also detect redundant values. | 2724 // We could also detect redundant values. |
2723 // The code could also randomize the order of values, though | 2725 // The code could also randomize the order of values, though |
2724 // that's tricky because vldr has a limited reach. Furthermore | 2726 // that's tricky because vldr has a limited reach. Furthermore |
2725 // it breaks load locality. | 2727 // it breaks load locality. |
2726 ConstantPoolAddEntry(pc_offset(), imm); | 2728 ConstantPoolEntry::Access access = ConstantPoolAddEntry(pc_offset(), imm); |
| 2729 DCHECK(access == ConstantPoolEntry::REGULAR); |
| 2730 USE(access); |
2727 vldr(dst, MemOperand(pc, 0)); | 2731 vldr(dst, MemOperand(pc, 0)); |
2728 } else { | 2732 } else { |
2729 // Synthesise the double from ARM immediates. | 2733 // Synthesise the double from ARM immediates. |
2730 uint32_t lo, hi; | 2734 uint32_t lo, hi; |
2731 DoubleAsTwoUInt32(imm, &lo, &hi); | 2735 DoubleAsTwoUInt32(imm, &lo, &hi); |
2732 | 2736 |
2733 if (lo == hi) { | 2737 if (lo == hi) { |
2734 // Move the low and high parts of the double to a D register in one | 2738 // Move the low and high parts of the double to a D register in one |
2735 // instruction. | 2739 // instruction. |
2736 mov(ip, Operand(lo)); | 2740 mov(ip, Operand(lo)); |
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5008 } | 5012 } |
5009 | 5013 |
5010 | 5014 |
5011 void Assembler::emit_code_stub_address(Code* stub) { | 5015 void Assembler::emit_code_stub_address(Code* stub) { |
5012 CheckBuffer(); | 5016 CheckBuffer(); |
5013 *reinterpret_cast<uint32_t*>(pc_) = | 5017 *reinterpret_cast<uint32_t*>(pc_) = |
5014 reinterpret_cast<uint32_t>(stub->instruction_start()); | 5018 reinterpret_cast<uint32_t>(stub->instruction_start()); |
5015 pc_ += sizeof(uint32_t); | 5019 pc_ += sizeof(uint32_t); |
5016 } | 5020 } |
5017 | 5021 |
| 5022 |
5018 void Assembler::RecordRelocInfo(RelocInfo::Mode rmode, intptr_t data) { | 5023 void Assembler::RecordRelocInfo(RelocInfo::Mode rmode, intptr_t data) { |
5019 if (RelocInfo::IsNone(rmode) || | 5024 if (RelocInfo::IsNone(rmode) || |
5020 // Don't record external references unless the heap will be serialized. | 5025 // Don't record external references unless the heap will be serialized. |
5021 (rmode == RelocInfo::EXTERNAL_REFERENCE && !serializer_enabled() && | 5026 (rmode == RelocInfo::EXTERNAL_REFERENCE && !serializer_enabled() && |
5022 !emit_debug_code())) { | 5027 !emit_debug_code())) { |
5023 return; | 5028 return; |
5024 } | 5029 } |
5025 DCHECK(buffer_space() >= kMaxRelocSize); // too late to grow buffer here | 5030 DCHECK(buffer_space() >= kMaxRelocSize); // too late to grow buffer here |
5026 if (rmode == RelocInfo::CODE_TARGET_WITH_ID) { | 5031 if (rmode == RelocInfo::CODE_TARGET_WITH_ID) { |
5027 data = RecordedAstId().ToInt(); | 5032 data = RecordedAstId().ToInt(); |
5028 ClearRecordedAstId(); | 5033 ClearRecordedAstId(); |
5029 } | 5034 } |
5030 RelocInfo rinfo(pc_, rmode, data, NULL); | 5035 RelocInfo rinfo(pc_, rmode, data, NULL); |
5031 reloc_info_writer.Write(&rinfo); | 5036 reloc_info_writer.Write(&rinfo); |
5032 } | 5037 } |
5033 | 5038 |
5034 void Assembler::ConstantPoolAddEntry(int position, RelocInfo::Mode rmode, | 5039 |
5035 intptr_t value) { | 5040 ConstantPoolEntry::Access Assembler::ConstantPoolAddEntry(int position, |
| 5041 RelocInfo::Mode rmode, |
| 5042 intptr_t value) { |
5036 DCHECK(rmode != RelocInfo::COMMENT && rmode != RelocInfo::CONST_POOL && | 5043 DCHECK(rmode != RelocInfo::COMMENT && rmode != RelocInfo::CONST_POOL && |
5037 rmode != RelocInfo::NONE64); | 5044 rmode != RelocInfo::NONE64); |
5038 bool sharing_ok = RelocInfo::IsNone(rmode) || | 5045 bool sharing_ok = RelocInfo::IsNone(rmode) || |
5039 (rmode >= RelocInfo::FIRST_SHAREABLE_RELOC_MODE); | 5046 !(serializer_enabled() || rmode < RelocInfo::CELL); |
5040 DCHECK(pending_32_bit_constants_.size() < kMaxNumPending32Constants); | 5047 DCHECK(pending_32_bit_constants_.size() < kMaxNumPending32Constants); |
5041 if (pending_32_bit_constants_.empty()) { | 5048 if (pending_32_bit_constants_.empty()) { |
5042 first_const_pool_32_use_ = position; | 5049 first_const_pool_32_use_ = position; |
5043 } | 5050 } |
5044 ConstantPoolEntry entry( | 5051 ConstantPoolEntry entry(position, value, sharing_ok); |
5045 position, value, | |
5046 sharing_ok || (rmode == RelocInfo::CODE_TARGET && serializer_enabled())); | |
5047 | |
5048 bool shared = false; | |
5049 if (sharing_ok) { | |
5050 // Merge the constant, if possible. | |
5051 for (size_t i = 0; i < pending_32_bit_constants_.size(); i++) { | |
5052 ConstantPoolEntry& current_entry = pending_32_bit_constants_[i]; | |
5053 if (!current_entry.sharing_ok()) continue; | |
5054 if (entry.value() == current_entry.value()) { | |
5055 entry.set_merged_index(i); | |
5056 shared = true; | |
5057 break; | |
5058 } | |
5059 } | |
5060 } | |
5061 | |
5062 if (rmode == RelocInfo::CODE_TARGET && serializer_enabled()) { | |
5063 // TODO(all): We only do this in the serializer, for now, because | |
5064 // full-codegen relies on RelocInfo for translating PCs between full-codegen | |
5065 // normal and debug code. | |
5066 // Sharing entries here relies on canonicalized handles - without them, we | |
5067 // will miss the optimisation opportunity. | |
5068 Address handle_address = reinterpret_cast<Address>(value); | |
5069 auto existing = handle_to_index_map_.find(handle_address); | |
5070 if (existing != handle_to_index_map_.end()) { | |
5071 int index = existing->second; | |
5072 entry.set_merged_index(index); | |
5073 shared = true; | |
5074 } else { | |
5075 // Keep track of this code handle. | |
5076 handle_to_index_map_[handle_address] = | |
5077 static_cast<int>(pending_32_bit_constants_.size()); | |
5078 } | |
5079 } | |
5080 | |
5081 pending_32_bit_constants_.push_back(entry); | 5052 pending_32_bit_constants_.push_back(entry); |
5082 | 5053 |
5083 // Make sure the constant pool is not emitted in place of the next | 5054 // Make sure the constant pool is not emitted in place of the next |
5084 // instruction for which we just recorded relocation info. | 5055 // instruction for which we just recorded relocation info. |
5085 BlockConstPoolFor(1); | 5056 BlockConstPoolFor(1); |
5086 | 5057 return ConstantPoolEntry::REGULAR; |
5087 // Emit relocation info. | |
5088 if (must_output_reloc_info(rmode, this) && !shared) { | |
5089 RecordRelocInfo(rmode); | |
5090 } | |
5091 } | 5058 } |
5092 | 5059 |
5093 void Assembler::ConstantPoolAddEntry(int position, double value) { | 5060 |
| 5061 ConstantPoolEntry::Access Assembler::ConstantPoolAddEntry(int position, |
| 5062 double value) { |
5094 DCHECK(pending_64_bit_constants_.size() < kMaxNumPending64Constants); | 5063 DCHECK(pending_64_bit_constants_.size() < kMaxNumPending64Constants); |
5095 if (pending_64_bit_constants_.empty()) { | 5064 if (pending_64_bit_constants_.empty()) { |
5096 first_const_pool_64_use_ = position; | 5065 first_const_pool_64_use_ = position; |
5097 } | 5066 } |
5098 ConstantPoolEntry entry(position, value); | 5067 ConstantPoolEntry entry(position, value); |
5099 | |
5100 // Merge the constant, if possible. | |
5101 for (size_t i = 0; i < pending_64_bit_constants_.size(); i++) { | |
5102 ConstantPoolEntry& current_entry = pending_64_bit_constants_[i]; | |
5103 DCHECK(current_entry.sharing_ok()); | |
5104 if (entry.value() == current_entry.value()) { | |
5105 entry.set_merged_index(i); | |
5106 break; | |
5107 } | |
5108 } | |
5109 pending_64_bit_constants_.push_back(entry); | 5068 pending_64_bit_constants_.push_back(entry); |
5110 | 5069 |
5111 // Make sure the constant pool is not emitted in place of the next | 5070 // Make sure the constant pool is not emitted in place of the next |
5112 // instruction for which we just recorded relocation info. | 5071 // instruction for which we just recorded relocation info. |
5113 BlockConstPoolFor(1); | 5072 BlockConstPoolFor(1); |
| 5073 return ConstantPoolEntry::REGULAR; |
5114 } | 5074 } |
5115 | 5075 |
5116 | 5076 |
5117 void Assembler::BlockConstPoolFor(int instructions) { | 5077 void Assembler::BlockConstPoolFor(int instructions) { |
5118 int pc_limit = pc_offset() + instructions * kInstrSize; | 5078 int pc_limit = pc_offset() + instructions * kInstrSize; |
5119 if (no_const_pool_before_ < pc_limit) { | 5079 if (no_const_pool_before_ < pc_limit) { |
5120 // Max pool start (if we need a jump and an alignment). | 5080 // Max pool start (if we need a jump and an alignment). |
5121 #ifdef DEBUG | 5081 #ifdef DEBUG |
5122 int start = pc_limit + kInstrSize + 2 * kPointerSize; | 5082 int start = pc_limit + kInstrSize + 2 * kPointerSize; |
5123 DCHECK(pending_32_bit_constants_.empty() || | 5083 DCHECK(pending_32_bit_constants_.empty() || |
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5204 need_emit = true; | 5164 need_emit = true; |
5205 } | 5165 } |
5206 } | 5166 } |
5207 if (!need_emit) return; | 5167 if (!need_emit) return; |
5208 } | 5168 } |
5209 | 5169 |
5210 // Deduplicate constants. | 5170 // Deduplicate constants. |
5211 int size_after_marker = estimated_size_after_marker; | 5171 int size_after_marker = estimated_size_after_marker; |
5212 for (size_t i = 0; i < pending_64_bit_constants_.size(); i++) { | 5172 for (size_t i = 0; i < pending_64_bit_constants_.size(); i++) { |
5213 ConstantPoolEntry& entry = pending_64_bit_constants_[i]; | 5173 ConstantPoolEntry& entry = pending_64_bit_constants_[i]; |
5214 if (entry.is_merged()) size_after_marker -= kDoubleSize; | 5174 DCHECK(!entry.is_merged()); |
| 5175 for (size_t j = 0; j < i; j++) { |
| 5176 if (entry.value64() == pending_64_bit_constants_[j].value64()) { |
| 5177 DCHECK(!pending_64_bit_constants_[j].is_merged()); |
| 5178 entry.set_merged_index(j); |
| 5179 size_after_marker -= kDoubleSize; |
| 5180 break; |
| 5181 } |
| 5182 } |
5215 } | 5183 } |
5216 | 5184 |
5217 for (size_t i = 0; i < pending_32_bit_constants_.size(); i++) { | 5185 for (size_t i = 0; i < pending_32_bit_constants_.size(); i++) { |
5218 ConstantPoolEntry& entry = pending_32_bit_constants_[i]; | 5186 ConstantPoolEntry& entry = pending_32_bit_constants_[i]; |
5219 if (entry.is_merged()) size_after_marker -= kPointerSize; | 5187 DCHECK(!entry.is_merged()); |
| 5188 if (!entry.sharing_ok()) continue; |
| 5189 for (size_t j = 0; j < i; j++) { |
| 5190 if (entry.value() == pending_32_bit_constants_[j].value()) { |
| 5191 DCHECK(!pending_32_bit_constants_[j].is_merged()); |
| 5192 entry.set_merged_index(j); |
| 5193 size_after_marker -= kPointerSize; |
| 5194 break; |
| 5195 } |
| 5196 } |
5220 } | 5197 } |
5221 | 5198 |
5222 int size = size_up_to_marker + size_after_marker; | 5199 int size = size_up_to_marker + size_after_marker; |
5223 | 5200 |
5224 int needed_space = size + kGap; | 5201 int needed_space = size + kGap; |
5225 while (buffer_space() <= needed_space) GrowBuffer(); | 5202 while (buffer_space() <= needed_space) GrowBuffer(); |
5226 | 5203 |
5227 { | 5204 { |
5228 // Block recursive calls to CheckConstPool. | 5205 // Block recursive calls to CheckConstPool. |
5229 BlockConstPoolScope block_const_pool(this); | 5206 BlockConstPoolScope block_const_pool(this); |
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5308 } | 5285 } |
5309 instr_at_put(entry.position(), | 5286 instr_at_put(entry.position(), |
5310 SetLdrRegisterImmediateOffset(instr, delta)); | 5287 SetLdrRegisterImmediateOffset(instr, delta)); |
5311 if (!entry.is_merged()) { | 5288 if (!entry.is_merged()) { |
5312 emit(entry.value()); | 5289 emit(entry.value()); |
5313 } | 5290 } |
5314 } | 5291 } |
5315 | 5292 |
5316 pending_32_bit_constants_.clear(); | 5293 pending_32_bit_constants_.clear(); |
5317 pending_64_bit_constants_.clear(); | 5294 pending_64_bit_constants_.clear(); |
5318 handle_to_index_map_.clear(); | |
5319 | |
5320 first_const_pool_32_use_ = -1; | 5295 first_const_pool_32_use_ = -1; |
5321 first_const_pool_64_use_ = -1; | 5296 first_const_pool_64_use_ = -1; |
5322 | 5297 |
5323 RecordComment("]"); | 5298 RecordComment("]"); |
5324 | 5299 |
5325 DCHECK_EQ(size, SizeOfCodeGeneratedSince(&size_check)); | 5300 DCHECK_EQ(size, SizeOfCodeGeneratedSince(&size_check)); |
5326 | 5301 |
5327 if (after_pool.is_linked()) { | 5302 if (after_pool.is_linked()) { |
5328 bind(&after_pool); | 5303 bind(&after_pool); |
5329 } | 5304 } |
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5355 } | 5330 } |
5356 | 5331 |
5357 void PatchingAssembler::FlushICache(Isolate* isolate) { | 5332 void PatchingAssembler::FlushICache(Isolate* isolate) { |
5358 Assembler::FlushICache(isolate, buffer_, buffer_size_ - kGap); | 5333 Assembler::FlushICache(isolate, buffer_, buffer_size_ - kGap); |
5359 } | 5334 } |
5360 | 5335 |
5361 } // namespace internal | 5336 } // namespace internal |
5362 } // namespace v8 | 5337 } // namespace v8 |
5363 | 5338 |
5364 #endif // V8_TARGET_ARCH_ARM | 5339 #endif // V8_TARGET_ARCH_ARM |
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