| Index: src/IceTargetLoweringARM32.cpp
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| diff --git a/src/IceTargetLoweringARM32.cpp b/src/IceTargetLoweringARM32.cpp
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| index 7e67b71d259fc54a965dfbca3efc23f54c5a9fa3..db0ea1de7a1e7b1dc04d1ae39e149389117b6bb1 100644
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| --- a/src/IceTargetLoweringARM32.cpp
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| +++ b/src/IceTargetLoweringARM32.cpp
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| @@ -386,18 +386,18 @@ bool TargetARM32::doBranchOpt(Inst *I, const CfgNode *NextNode) {
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|    return false;
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|  }
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|  
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| -IceString TargetARM32::getRegName(SizeT RegNum, Type Ty) const {
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| -  assert(RegNum < RegARM32::Reg_NUM);
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| -  (void)Ty;
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| -  static const char *RegNames[] = {
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| +const char *RegARM32::RegNames[] = {
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|  #define X(val, encode, name, scratch, preserved, stackptr, frameptr, isInt,    \
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|            isI64Pair, isFP32, isFP64, isVec128, alias_init)                     \
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|    name,
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| -      REGARM32_TABLE
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| +    REGARM32_TABLE
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|  #undef X
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| -  };
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| +};
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|  
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| -  return RegNames[RegNum];
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| +IceString TargetARM32::getRegName(SizeT RegNum, Type Ty) const {
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| +  assert(RegNum < RegARM32::Reg_NUM);
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| +  (void)Ty;
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| +  return RegARM32::RegNames[RegNum];
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|  }
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|  
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|  Variable *TargetARM32::getPhysicalRegister(SizeT RegNum, Type Ty) {
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| 
 |