Handle MOV (immediate) and MOVT to load ARM global addresses.

src/IceTargetLoweringARM32.cpp

 //===- subzero/src/IceTargetLoweringARM32.cpp - ARM32 lowering ------------===//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 ///
 /// \file
@@ skipping 368 matching lines @@
   }
 }
 
 bool TargetARM32::doBranchOpt(Inst *I, const CfgNode *NextNode) {
   if (InstARM32Br *Br = llvm::dyn_cast<InstARM32Br>(I)) {
     return Br->optimizeBranch(NextNode);
   }
   return false;
 }
 
+const char *RegARM32::RegNames[] = {
+#define X(val, encode, name, scratch, preserved, stackptr, frameptr, isInt,    \
+          isI64Pair, isFP32, isFP64, isVec128, alias_init)                     \
+  name,
+    REGARM32_TABLE
+#undef X
+};
+
 IceString TargetARM32::getRegName(SizeT RegNum, Type Ty) const {
   assert(RegNum < RegARM32::Reg_NUM);
   (void)Ty;
-  static const char *RegNames[] = {
-#define X(val, encode, name, scratch, preserved, stackptr, frameptr, isInt,    \
-          isI64Pair, isFP32, isFP64, isVec128, alias_init)                     \
-  name,
-      REGARM32_TABLE
-#undef X
-  };
-
-  return RegNames[RegNum];
+  return RegARM32::RegNames[RegNum];
 }
 
 Variable *TargetARM32::getPhysicalRegister(SizeT RegNum, Type Ty) {
   static const Type DefaultType[] = {
 #define X(val, encode, name, scratch, preserved, stackptr, frameptr, isInt,    \
           isI64Pair, isFP32, isFP64, isVec128, alias_init)                     \
   (isFP32)                                                                     \
       ? IceType_f32                                                            \
       : ((isFP64) ? IceType_f64 : ((isVec128 ? IceType_v4i32 : IceType_i32))),
       REGARM32_TABLE
@@ skipping 3543 matching lines @@
       << ".eabi_attribute 68, 1   @ Tag_Virtualization_use\n";
   if (CPUFeatures.hasFeature(TargetARM32Features::HWDivArm)) {
     Str << ".eabi_attribute 44, 2   @ Tag_DIV_use\n";
   }
   // Technically R9 is used for TLS with Sandboxing, and we reserve it.
   // However, for compatibility with current NaCl LLVM, don't claim that.
   Str << ".eabi_attribute 14, 3   @ Tag_ABI_PCS_R9_use: Not used\n";
 }
 
 } // end of namespace Ice