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Unified Diff: src/IceInstX8664.def

Issue 1419903002: Subzero: Refactor x86 register definitions to use the alias mechanism. (Closed) Base URL: https://chromium.googlesource.com/native_client/pnacl-subzero.git@master
Patch Set: Fix assembler unit tests. Fix register names. Code review changes. Rebase Created 5 years, 2 months ago
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Index: src/IceInstX8664.def
diff --git a/src/IceInstX8664.def b/src/IceInstX8664.def
index 7ad1eaa125fb5d63a0b99b237a71c397c792e9a0..b3f452f438036d2acd1ae25e0b49011eaa6eab6e 100644
--- a/src/IceInstX8664.def
+++ b/src/IceInstX8664.def
@@ -15,146 +15,299 @@
#ifndef SUBZERO_SRC_ICEINSTX8664_DEF
#define SUBZERO_SRC_ICEINSTX8664_DEF
-// NOTE: we use the 32bit register names for two reasons:
-// (1) it makes it easier to implement the x86 assembler template.
-// (2) when generating code, subzero defaults to using 32 bit registers,
-// so using the 32 bit register name would hopefully make this design
-// more explicit.
-// NOTE: esp is not considered isInt, to avoid register allocating it.
+#include "IceRegList.h"
+
+// x86-64 ABI:
+// Scratch GPRs: rax, rcx, rdx, rsi, rdi, r8, r9, r10, r11
+// Callee-save GPRs: rbx, rbp, r12, r13, r14, r15
+// Scratch XMMs: xmm0, xmm1, xmm2, xmm3, xmm4, xmm5, xmm6, xmm7,
+// xmm8, xmm9, xmm10, xmm11, xmm12, xmm13, xmm14, xmm15
+// Key to table columns:
+// val: Enum value, when a specific register is needed during lowering.
+// encode: Encoding in the integrated assembler.
+// name: Name used for the external assembler.
+// scratch: Scratch (caller-save) register.
+// preserved: Preserved (callee-save) register.
+// stackptr: This register is used as the stack pointer.
+// frameptr: This register is used as the frame pointer if needed.
+// isGPR: This is a GPR (integer-type).
+// is64: This is a 64-bit GPR.
+// is32: This is a 32-bit GPR.
+// is16: This is a 16-bit GPR.
+// is8: This is an 8-bit GPR.
+// isXmm: This is an XMM register for FP and vector ops.
+// is64To8: A 64-bit GPR truncable to 8-bit.
+// is32To8: A 32-bit GPR truncable to 8-bit.
+// is16To8: A 16-bit GPR truncable to 8-bit.
+// isTrunc8Rcvr: An 8-bit GPR that a wider GPR trivially truncates to.
+// isAhRcvr: An 8-bit GPR that register "ah" can be assigned to.
+// aliases: List of register aliases, which need not include this register.
+#define REGX8664_BYTEREG_TABLE \
+ /* val, encode, name, base, scratch,preserved,stackptr,frameptr, \
+ isGPR,is64,is32,is16,is8, isXmm, \
+ is64To8,is32To8,is16To8,isTrunc8Rcvr,isAhRcvr, aliases */ \
+ /* 8-bit registers */ \
+ X(Reg_al, 0, "al", Reg_eax, 1,0,0,0, 1,0,0,0,1, 0, 0,0,0,1,1, \
+ REGLIST3(RegX8664, rax, eax, ax)) \
+ X(Reg_cl, 1, "cl", Reg_ecx, 1,0,0,0, 1,0,0,0,1, 0, 0,0,0,1,1, \
+ REGLIST3(RegX8664, rcx, ecx, cx)) \
+ X(Reg_dl, 2, "dl", Reg_edx, 1,0,0,0, 1,0,0,0,1, 0, 0,0,0,1,1, \
+ REGLIST3(RegX8664, rdx, edx, dx)) \
+ X(Reg_bl, 3, "bl", Reg_ebx, 0,1,0,0, 1,0,0,0,1, 0, 0,0,0,1,1, \
+ REGLIST3(RegX8664, rbx, ebx, bx)) \
+ X(Reg_spl, 4, "spl", Reg_esp, 0,0,1,0, 1,0,0,0,0, 0, 0,0,0,0,0, \
+ REGLIST3(RegX8664, rsp, esp, sp)) \
+ X(Reg_bpl, 5, "bpl", Reg_ebp, 0,1,0,1, 1,0,0,0,1, 0, 0,0,0,1,0, \
+ REGLIST3(RegX8664, rbp, ebp, bp)) \
+ X(Reg_sil, 6, "sil", Reg_esi, 1,0,0,0, 1,0,0,0,1, 0, 0,0,0,1,0, \
+ REGLIST3(RegX8664, rsi, esi, si)) \
+ X(Reg_dil, 7, "dil", Reg_edi, 1,0,0,0, 1,0,0,0,1, 0, 0,0,0,1,0, \
+ REGLIST3(RegX8664, rdi, edi, di)) \
+ X(Reg_r8l, 8, "r8b", Reg_r8, 1,0,0,0, 1,0,0,0,1, 0, 0,0,0,1,0, \
+ REGLIST3(RegX8664, r8, r8d, r8w)) \
+ X(Reg_r9l, 9, "r9b", Reg_r9, 1,0,0,0, 1,0,0,0,1, 0, 0,0,0,1,0, \
+ REGLIST3(RegX8664, r9, r9d, r9w)) \
+ X(Reg_r10l, 10, "r10b", Reg_r10, 1,0,0,1, 0,0,0,0,1, 0, 0,0,0,1,0, \
+ REGLIST3(RegX8664, r10, r10d, r10w)) \
+ X(Reg_r11l, 11, "r11b", Reg_r11, 1,0,0,1, 0,0,0,0,1, 0, 0,0,0,1,0, \
+ REGLIST3(RegX8664, r11, r11d, r11w)) \
+ X(Reg_r12l, 12, "r12b", Reg_r12, 0,1,0,1, 0,0,0,0,1, 0, 0,0,0,1,0, \
+ REGLIST3(RegX8664, r12, r12d, r12w)) \
+ X(Reg_r13l, 13, "r13b", Reg_r13, 0,1,0,1, 0,0,0,0,1, 0, 0,0,0,1,0, \
+ REGLIST3(RegX8664, r13, r13d, r13w)) \
+ X(Reg_r14l, 14, "r14b", Reg_r14, 0,1,0,1, 0,0,0,0,1, 0, 0,0,0,1,0, \
+ REGLIST3(RegX8664, r14, r14d, r14w)) \
+ X(Reg_r15l, 15, "r15b", Reg_r15, 0,1,0,1, 0,0,0,0,1, 0, 0,0,0,1,0, \
+ REGLIST3(RegX8664, r15, r15d, r15w)) \
+ /* High 8-bit registers. None are allowed for register allocation. */ \
+ X(Reg_ah, 4, "ah", Reg_eax, 1,0,0,0, 1,0,0,0,0, 0, 0,0,0,0,1, \
+ REGLIST3(RegX8664, rax, eax, ax)) \
+ X(Reg_ch, 5, "ch", Reg_ecx, 1,0,0,0, 1,0,0,0,0, 0, 0,0,0,0,1, \
+ REGLIST3(RegX8664, rcx, ecx, cx)) \
+ X(Reg_dh, 6, "dh", Reg_edx, 1,0,0,0, 1,0,0,0,0, 0, 0,0,0,0,1, \
+ REGLIST3(RegX8664, rdx, edx, dx)) \
+ X(Reg_bh, 7, "bh", Reg_ebx, 0,1,0,0, 1,0,0,0,0, 0, 0,0,0,0,1, \
+ REGLIST3(RegX8664, rbx, ebx, bx)) \
+ /* End of 8-bit register set */
+//#define X(val, encode, name, base, scratch, preserved, stackptr, frameptr,
+// isGPR, is64, is32, is16, is8, isXmm, is64To8, is32To8, is16To8,
+// isTrunc8Rcvr, isAhRcvr, aliases)
+
#define REGX8664_GPR_TABLE \
- /* val, encode, name64, name, name16, name8, scratch, preserved, stackptr, \
- frameptr, isInt, isFP */ \
- X(Reg_eax, = 0, "rax", "eax" , "ax" , "al" , 1, 0, 0, 0, 1, 0) \
- X(Reg_ecx, = 1, "rcx", "ecx" , "cx" , "cl" , 1, 0, 0, 0, 1, 0) \
- X(Reg_edx, = 2, "rdx", "edx" , "dx" , "dl" , 1, 0, 0, 0, 1, 0) \
- X(Reg_ebx, = 3, "rbx", "ebx" , "bx" , "bl" , 0, 1, 0, 0, 1, 0) \
- X(Reg_esp, = 4, "rsp", "esp" , "sp" , "spl" , 0, 0, 1, 0, 0, 0) \
- X(Reg_ebp, = 5, "rbp", "ebp" , "bp" , "bpl" , 0, 0, 0, 1, 1, 0) \
- X(Reg_esi, = 6, "rsi", "esi" , "si" , "sil" , 1, 0, 0, 0, 1, 0) \
- X(Reg_edi, = 7, "rdi", "edi" , "di" , "dil" , 1, 0, 0, 0, 1, 0) \
- X(Reg_r8d, = 8, "r8" , "r8d" , "r8w", "r8l" , 1, 0, 0, 0, 1, 0) \
- X(Reg_r9d, = 9, "r9" , "r9d" , "r9w", "r9l" , 1, 0, 0, 0, 1, 0) \
- X(Reg_r10d, = 10, "r10", "r10d", "r10w", "r10l", 1, 0, 0, 0, 1, 0) \
- X(Reg_r11d, = 11, "r11", "r11d", "r11w", "r11l", 1, 0, 0, 0, 1, 0) \
- X(Reg_r12d, = 12, "r12", "r12d", "r12w", "r12l", 0, 1, 0, 0, 1, 0) \
- X(Reg_r13d, = 13, "r13", "r13d", "r13w", "r12l", 0, 1, 0, 0, 1, 0) \
- X(Reg_r14d, = 14, "r14", "r14d", "r14w", "r14l", 0, 1, 0, 0, 1, 0) \
- X(Reg_r15d, = 15, "r15", "r15d", "r15w", "r15l", 0, 1, 0, 0, 1, 0)
+ /* val, encode, name, base, scratch,preserved,stackptr,frameptr, \
+ isGPR,is64,is32,is16,is8, isXmm, \
+ is64To8,is32To8,is16To8,isTrunc8Rcvr,isAhRcvr, aliases */ \
+ /* 64-bit registers */ \
+ X(Reg_rax, 0, "rax", Reg_rax, 1,0,0,0, 1,1,0,0,0, 0, 0,0,0,0,0, \
+ REGLIST4(RegX8664, eax, ax, al, ah)) \
+ X(Reg_rcx, 1, "rcx", Reg_rcx, 1,0,0,0, 1,1,0,0,0, 0, 0,0,0,0,0, \
+ REGLIST4(RegX8664, ecx, cx, cl, ch)) \
+ X(Reg_rdx, 2, "rdx", Reg_rdx, 1,0,0,0, 1,1,0,0,0, 0, 0,0,0,0,0, \
+ REGLIST4(RegX8664, edx, dx, dl, dh)) \
+ X(Reg_rbx, 3, "rbx", Reg_rbx, 0,1,0,0, 1,1,0,0,0, 0, 0,0,0,0,0, \
+ REGLIST4(RegX8664, ebx, bx, bl, bh)) \
+ X(Reg_rsp, 4, "rsp", Reg_rsp, 0,0,1,0, 1,0,0,0,0, 0, 0,0,0,0,0, \
+ REGLIST3(RegX8664, esp, sp, spl)) \
+ X(Reg_rbp, 5, "rbp", Reg_rbp, 0,1,0,1, 1,1,0,0,0, 0, 0,0,0,0,0, \
+ REGLIST3(RegX8664, ebp, bp, bpl)) \
+ X(Reg_rsi, 6, "rsi", Reg_rsi, 1,0,0,0, 1,1,0,0,0, 0, 0,0,0,0,0, \
+ REGLIST3(RegX8664, esi, si, sil)) \
+ X(Reg_rdi, 7, "rdi", Reg_rdi, 1,0,0,0, 1,1,0,0,0, 0, 0,0,0,0,0, \
+ REGLIST3(RegX8664, edi, di, dil)) \
+ X(Reg_r8, 8, "r8", Reg_r8, 1,0,0,0, 1,1,0,0,0, 0, 0,0,0,0,0, \
+ REGLIST3(RegX8664, r8d, r8w, r8l)) \
+ X(Reg_r9, 9, "r9", Reg_r9, 1,0,0,0, 1,1,0,0,0, 0, 0,0,0,0,0, \
+ REGLIST3(RegX8664, r9d, r9w, r9l)) \
+ X(Reg_r10, 10, "r10", Reg_r10, 1,0,0,0, 1,1,0,0,0, 0, 0,0,0,0,0, \
+ REGLIST3(RegX8664, r10d, r10w, r10l)) \
+ X(Reg_r11, 11, "r11", Reg_r11, 1,0,0,0, 1,1,0,0,0, 0, 0,0,0,0,0, \
+ REGLIST3(RegX8664, r11d, r11w, r11l)) \
+ X(Reg_r12, 12, "r12", Reg_r12, 0,1,0,0, 1,1,0,0,0, 0, 0,0,0,0,0, \
+ REGLIST3(RegX8664, r12d, r12w, r12l)) \
+ X(Reg_r13, 13, "r13", Reg_r13, 0,1,0,0, 1,1,0,0,0, 0, 0,0,0,0,0, \
+ REGLIST3(RegX8664, r13d, r13w, r13l)) \
+ X(Reg_r14, 14, "r14", Reg_r14, 0,1,0,0, 1,1,0,0,0, 0, 0,0,0,0,0, \
+ REGLIST3(RegX8664, r14d, r14w, r14l)) \
+ X(Reg_r15, 15, "r15", Reg_r15, 0,1,0,0, 1,1,0,0,0, 0, 0,0,0,0,0, \
+ REGLIST3(RegX8664, r15d, r15w, r15l)) \
+ /* 32-bit registers */ \
+ X(Reg_eax, 0, "eax", Reg_eax, 1,0,0,0, 1,0,1,0,0, 0, 0,1,0,0,0, \
+ REGLIST4(RegX8664, rax, ax, al, ah)) \
+ X(Reg_ecx, 1, "ecx", Reg_ecx, 1,0,0,0, 1,0,1,0,0, 0, 0,1,0,0,0, \
+ REGLIST4(RegX8664, rcx, cx, cl, ch)) \
+ X(Reg_edx, 2, "edx", Reg_edx, 1,0,0,0, 1,0,1,0,0, 0, 0,1,0,0,0, \
+ REGLIST4(RegX8664, rdx, dx, dl, dh)) \
+ X(Reg_ebx, 3, "ebx", Reg_ebx, 0,1,0,0, 1,0,1,0,0, 0, 0,1,0,0,0, \
+ REGLIST4(RegX8664, rbx, bx, bl, bh)) \
+ X(Reg_esp, 4, "esp", Reg_esp, 0,0,1,0, 1,0,0,0,0, 0, 0,0,0,0,0, \
+ REGLIST3(RegX8664, rsp, sp, spl)) \
+ X(Reg_ebp, 5, "ebp", Reg_ebp, 0,1,0,1, 1,0,1,0,0, 0, 0,1,0,0,0, \
+ REGLIST3(RegX8664, rbp, bp, bpl)) \
+ X(Reg_esi, 6, "esi", Reg_esi, 1,0,0,0, 1,0,1,0,0, 0, 0,1,0,0,0, \
+ REGLIST3(RegX8664, rsi, si, sil)) \
+ X(Reg_edi, 7, "edi", Reg_edi, 1,0,0,0, 1,0,1,0,0, 0, 0,1,0,0,0, \
+ REGLIST3(RegX8664, rdi, di, dil)) \
+ X(Reg_r8d, 8, "r8d", Reg_r8, 1,0,0,0, 1,0,1,0,0, 0, 0,1,0,0,0, \
+ REGLIST3(RegX8664, r8, r8w, r8l)) \
+ X(Reg_r9d, 9, "r9d", Reg_r9, 1,0,0,0, 1,0,1,0,0, 0, 0,1,0,0,0, \
+ REGLIST3(RegX8664, r9, r9w, r9l)) \
+ X(Reg_r10d, 10, "r10d", Reg_r10, 1,0,0,1, 0,0,1,0,0, 0, 0,1,0,0,0, \
+ REGLIST3(RegX8664, r10, r10w, r10l)) \
+ X(Reg_r11d, 11, "r11d", Reg_r11, 1,0,0,0, 1,0,1,0,0, 0, 0,1,0,0,0, \
+ REGLIST3(RegX8664, r11, r11w, r11l)) \
+ X(Reg_r12d, 12, "r12d", Reg_r12, 0,1,0,0, 1,0,1,0,0, 0, 0,1,0,0,0, \
+ REGLIST3(RegX8664, r12, r12w, r12l)) \
+ X(Reg_r13d, 13, "r13d", Reg_r13, 0,1,0,0, 1,0,1,0,0, 0, 0,1,0,0,0, \
+ REGLIST3(RegX8664, r13, r13w, r13l)) \
+ X(Reg_r14d, 14, "r14d", Reg_r14, 0,1,0,0, 1,0,1,0,0, 0, 0,1,0,0,0, \
+ REGLIST3(RegX8664, r14, r14w, r14l)) \
+ X(Reg_r15d, 15, "r15d", Reg_r15, 0,1,0,0, 1,0,1,0,0, 0, 0,1,0,0,0, \
+ REGLIST3(RegX8664, r15, r15w, r15l)) \
+ /* 16-bit registers */ \
+ X(Reg_ax, 0, "ax", Reg_eax, 1,0,0,0, 1,0,0,1,0, 0, 0,0,1,0,0, \
+ REGLIST4(RegX8664, rax, eax, al, ah)) \
+ X(Reg_cx, 1, "cx", Reg_ecx, 1,0,0,0, 1,0,0,1,0, 0, 0,0,1,0,0, \
+ REGLIST4(RegX8664, rcx, ecx, cl, ch)) \
+ X(Reg_dx, 2, "dx", Reg_edx, 1,0,0,0, 1,0,0,1,0, 0, 0,0,1,0,0, \
+ REGLIST4(RegX8664, rdx, edx, dl, dh)) \
+ X(Reg_bx, 3, "bx", Reg_ebx, 0,1,0,0, 1,0,0,1,0, 0, 0,0,1,0,0, \
+ REGLIST4(RegX8664, rbx, ebx, bl, bh)) \
+ X(Reg_sp, 4, "sp", Reg_esp, 0,0,1,0, 1,0,0,0,0, 0, 0,0,0,0,0, \
+ REGLIST3(RegX8664, rsp, esp, spl)) \
+ X(Reg_bp, 5, "bp", Reg_ebp, 0,1,0,1, 1,0,0,1,0, 0, 0,0,1,0,0, \
+ REGLIST3(RegX8664, rbp, ebp, bpl)) \
+ X(Reg_si, 6, "si", Reg_esi, 1,0,0,0, 1,0,0,1,0, 0, 0,0,1,0,0, \
+ REGLIST3(RegX8664, rsi, esi, sil)) \
+ X(Reg_di, 7, "di", Reg_edi, 1,0,0,0, 1,0,0,1,0, 0, 0,0,1,0,0, \
+ REGLIST3(RegX8664, rdi, edi, dil)) \
+ X(Reg_r8w, 8, "r8w", Reg_r8, 1,0,0,0, 1,0,0,1,0, 0, 0,0,1,0,0, \
+ REGLIST3(RegX8664, r8, r8d, r8l)) \
+ X(Reg_r9w, 9, "r9w", Reg_r9, 1,0,0,0, 1,0,0,1,0, 0, 0,0,1,0,0, \
+ REGLIST3(RegX8664, r9, r9d, r9l)) \
+ X(Reg_r10w, 10, "r10w", Reg_r10, 1,0,0,0, 1,0,0,1,0, 0, 0,0,1,0,0, \
+ REGLIST3(RegX8664, r10, r10d, r10l)) \
+ X(Reg_r11w, 11, "r11w", Reg_r11, 1,0,0,0, 1,0,0,1,0, 0, 0,0,1,0,0, \
+ REGLIST3(RegX8664, r11, r11d, r11l)) \
+ X(Reg_r12w, 12, "r12w", Reg_r12, 0,1,0,0, 1,0,0,1,0, 0, 0,0,1,0,0, \
+ REGLIST3(RegX8664, r12, r12d, r12l)) \
+ X(Reg_r13w, 13, "r13w", Reg_r13, 0,1,0,0, 1,0,0,1,0, 0, 0,0,1,0,0, \
+ REGLIST3(RegX8664, r13, r13d, r13l)) \
+ X(Reg_r14w, 14, "r14w", Reg_r14, 0,1,0,0, 1,0,0,1,0, 0, 0,0,1,0,0, \
+ REGLIST3(RegX8664, r14, r14d, r14l)) \
+ X(Reg_r15w, 15, "r15w", Reg_r15, 0,1,0,0, 1,0,0,1,0, 0, 0,0,1,0,0, \
+ REGLIST3(RegX8664, r15, r15d, r15l)) \
+ /* 8-bit registers */ \
+ REGX8664_BYTEREG_TABLE \
+ /* End of GPR register set */
+//#define X(val, encode, name, base, scratch, preserved, stackptr, frameptr,
+// isGPR, is64, is32, is16, is8, isXmm, is64To8, is32To8, is16To8,
+// isTrunc8Rcvr, isAhRcvr, aliases)
+// Note: It would be more appropriate to list the xmm register aliases as
+// REGLIST0(), but the corresponding empty initializer gives a syntax error, so
+// we use REGLIST1() to redundantly assign the register itself as an alias.
#define REGX8664_XMM_TABLE \
- /* val, encode, name64, name, name16, name8, scratch, preserved, stackptr, \
- frameptr, isInt, isFP */ \
- X(Reg_xmm0, = 0, "xmm0" , "", "", "", 1, 0, 0, 0, 0, 1) \
- X(Reg_xmm1, = 1, "xmm1" , "", "", "", 1, 0, 0, 0, 0, 1) \
- X(Reg_xmm2, = 2, "xmm2" , "", "", "", 1, 0, 0, 0, 0, 1) \
- X(Reg_xmm3, = 3, "xmm3" , "", "", "", 1, 0, 0, 0, 0, 1) \
- X(Reg_xmm4, = 4, "xmm4" , "", "", "", 1, 0, 0, 0, 0, 1) \
- X(Reg_xmm5, = 5, "xmm5" , "", "", "", 1, 0, 0, 0, 0, 1) \
- X(Reg_xmm6, = 6, "xmm6" , "", "", "", 1, 0, 0, 0, 0, 1) \
- X(Reg_xmm7, = 7, "xmm7" , "", "", "", 1, 0, 0, 0, 0, 1) \
- X(Reg_xmm8, = 8, "xmm8" , "", "", "", 1, 0, 0, 0, 0, 1) \
- X(Reg_xmm9, = 9, "xmm9" , "", "", "", 1, 0, 0, 0, 0, 1) \
- X(Reg_xmm10, = 10, "xmm10", "", "", "", 1, 0, 0, 0, 0, 1) \
- X(Reg_xmm11, = 11, "xmm11", "", "", "", 1, 0, 0, 0, 0, 1) \
- X(Reg_xmm12, = 12, "xmm12", "", "", "", 1, 0, 0, 0, 0, 1) \
- X(Reg_xmm13, = 13, "xmm13", "", "", "", 1, 0, 0, 0, 0, 1) \
- X(Reg_xmm14, = 14, "xmm14", "", "", "", 1, 0, 0, 0, 0, 1) \
- X(Reg_xmm15, = 15, "xmm15", "", "", "", 1, 0, 0, 0, 0, 1)
-//#define X(val, encode, name, name32, name16, name8, scratch, preserved,
-// stackptr, frameptr, isI8, isInt, isFP)
+ /* val, encode, name, base, scratch,preserved,stackptr,frameptr, \
+ isGPR,is64,is32,is16,is8, isXmm, \
+ is64To8,is32To8,is16To8,isTrunc8Rcvr,isAhRcvr, aliases */ \
+ /* xmm registers */ \
+ X(Reg_xmm0, 0, "xmm0", Reg_xmm0, 1,0,0,0, 0,0,0,0,0, 1, 0,0,0,0,0, \
+ REGLIST1(RegX8664, xmm0)) \
+ X(Reg_xmm1, 1, "xmm1", Reg_xmm1, 1,0,0,0, 0,0,0,0,0, 1, 0,0,0,0,0, \
+ REGLIST1(RegX8664, xmm1)) \
+ X(Reg_xmm2, 2, "xmm2", Reg_xmm2, 1,0,0,0, 0,0,0,0,0, 1, 0,0,0,0,0, \
+ REGLIST1(RegX8664, xmm2)) \
+ X(Reg_xmm3, 3, "xmm3", Reg_xmm3, 1,0,0,0, 0,0,0,0,0, 1, 0,0,0,0,0, \
+ REGLIST1(RegX8664, xmm3)) \
+ X(Reg_xmm4, 4, "xmm4", Reg_xmm4, 1,0,0,0, 0,0,0,0,0, 1, 0,0,0,0,0, \
+ REGLIST1(RegX8664, xmm4)) \
+ X(Reg_xmm5, 5, "xmm5", Reg_xmm5, 1,0,0,0, 0,0,0,0,0, 1, 0,0,0,0,0, \
+ REGLIST1(RegX8664, xmm5)) \
+ X(Reg_xmm6, 6, "xmm6", Reg_xmm6, 1,0,0,0, 0,0,0,0,0, 1, 0,0,0,0,0, \
+ REGLIST1(RegX8664, xmm6)) \
+ X(Reg_xmm7, 7, "xmm7", Reg_xmm7, 1,0,0,0, 0,0,0,0,0, 1, 0,0,0,0,0, \
+ REGLIST1(RegX8664, xmm7)) \
+ X(Reg_xmm8, 8, "xmm8", Reg_xmm8, 1,0,0,0, 0,0,0,0,0, 1, 0,0,0,0,0, \
+ REGLIST1(RegX8664, xmm8)) \
+ X(Reg_xmm9, 9, "xmm9", Reg_xmm9, 1,0,0,0, 0,0,0,0,0, 1, 0,0,0,0,0, \
+ REGLIST1(RegX8664, xmm9)) \
+ X(Reg_xmm10, 10, "xmm10", Reg_xmm10, 1,0,0,0, 0,0,0,0,0, 1, 0,0,0,0,0, \
+ REGLIST1(RegX8664, xmm10)) \
+ X(Reg_xmm11, 11, "xmm11", Reg_xmm11, 1,0,0,0, 0,0,0,0,0, 1, 0,0,0,0,0, \
+ REGLIST1(RegX8664, xmm11)) \
+ X(Reg_xmm12, 12, "xmm12", Reg_xmm12, 1,0,0,0, 0,0,0,0,0, 1, 0,0,0,0,0, \
+ REGLIST1(RegX8664, xmm12)) \
+ X(Reg_xmm13, 13, "xmm13", Reg_xmm13, 1,0,0,0, 0,0,0,0,0, 1, 0,0,0,0,0, \
+ REGLIST1(RegX8664, xmm13)) \
+ X(Reg_xmm14, 14, "xmm14", Reg_xmm14, 1,0,0,0, 0,0,0,0,0, 1, 0,0,0,0,0, \
+ REGLIST1(RegX8664, xmm14)) \
+ X(Reg_xmm15, 15, "xmm15", Reg_xmm15, 1,0,0,0, 0,0,0,0,0, 1, 0,0,0,0,0, \
+ REGLIST1(RegX8664, xmm15)) \
+ /* End of xmm register set */
+//#define X(val, encode, name, base, scratch, preserved, stackptr, frameptr,
+// isGPR, is64, is32, is16, is8, isXmm, is64To8, is32To8, is16To8,
+// isTrunc8Rcvr, isAhRcvr, aliases)
// We also provide a combined table, so that there is a namespace where
// all of the registers are considered and have distinct numberings.
// This is in contrast to the above, where the "encode" is based on how
// the register numbers will be encoded in binaries and values can overlap.
#define REGX8664_TABLE \
- /* val, encode, name64, name, name16, name8, scratch, preserved, \
- stackptr, frameptr, isInt, isFP */ \
REGX8664_GPR_TABLE \
REGX8664_XMM_TABLE
-//#define X(val, encode, name, name32, name16, name8, scratch, preserved,
-// stackptr, frameptr, isI8, isInt, isFP)
-
-#define REGX8664_TABLE_BOUNDS \
- /* val , init */ \
- X(Reg_GPR_First, = Reg_eax ) \
- X(Reg_GPR_Last , = Reg_r15d ) \
- X(Reg_XMM_First, = Reg_xmm0 ) \
- X(Reg_XMM_Last , = Reg_xmm15)
-// define X(val, init)
-
-// We also need the encodings for the Byte registers (other info overlaps
-// what is in the REGX8664_GPR_TABLE). We don't expose the ah, ch, dh,
-// bh registers to keep register selection simple.
-#define REGX8664_BYTEREG_TABLE \
- /* val , encode */ \
- X(Reg_al , = 0) \
- X(Reg_cl , = 1) \
- X(Reg_dl , = 2) \
- X(Reg_bl , = 3) \
- X(Reg_spl , = 4) \
- X(Reg_bpl , = 5) \
- X(Reg_sil , = 6) \
- X(Reg_dil , = 7) \
- X(Reg_r8l , = 8) \
- X(Reg_r9l , = 9) \
- X(Reg_r10l, = 10) \
- X(Reg_r11l, = 11) \
- X(Reg_r12l, = 12) \
- X(Reg_r13l, = 13) \
- X(Reg_r14l, = 14) \
- X(Reg_r15l, = 15)
-//#define X(val, encode)
+//#define X(val, encode, name, base, scratch, preserved, stackptr, frameptr,
+// isGPR, is64, is32, is16, is8, isXmm, is64To8, is32To8, is16To8,
+// isTrunc8Rcvr, isAhRcvr, aliases)
#define ICEINSTX8664BR_TABLE \
- /* enum value, encode, opposite, dump, emit */ \
- X(Br_o , = 0, Br_no , "o" , "jo" ) \
- X(Br_no , = 1, Br_o , "no", "jno") \
- X(Br_b , = 2, Br_ae , "b" , "jb" ) \
- X(Br_ae , = 3, Br_b , "ae", "jae") \
- X(Br_e , = 4, Br_ne , "e" , "je" ) \
- X(Br_ne , = 5, Br_e , "ne", "jne") \
- X(Br_be , = 6, Br_a , "be", "jbe") \
- X(Br_a , = 7, Br_be , "a" , "ja" ) \
- X(Br_s , = 8, Br_ns , "s" , "js" ) \
- X(Br_ns , = 9, Br_s , "ns", "jns") \
- X(Br_p , = 10, Br_np , "p" , "jp" ) \
- X(Br_np , = 11, Br_p , "np", "jnp") \
- X(Br_l , = 12, Br_ge , "l" , "jl" ) \
- X(Br_ge , = 13, Br_l , "ge", "jge") \
- X(Br_le , = 14, Br_g , "le", "jle") \
- X(Br_g , = 15, Br_le , "g" , "jg")
-//#define X(tag, encode, opp, dump, emit)
+ /* val, encode, opposite, dump, emit */ \
+ X(Br_o, 0, Br_no, "o", "jo") \
+ X(Br_no, 1, Br_o, "no", "jno") \
+ X(Br_b, 2, Br_ae, "b", "jb") \
+ X(Br_ae, 3, Br_b, "ae", "jae") \
+ X(Br_e, 4, Br_ne, "e", "je") \
+ X(Br_ne, 5, Br_e, "ne", "jne") \
+ X(Br_be, 6, Br_a, "be", "jbe") \
+ X(Br_a, 7, Br_be, "a", "ja") \
+ X(Br_s, 8, Br_ns, "s", "js") \
+ X(Br_ns, 9, Br_s, "ns", "jns") \
+ X(Br_p, 10, Br_np, "p", "jp") \
+ X(Br_np, 11, Br_p, "np", "jnp") \
+ X(Br_l, 12, Br_ge, "l", "jl") \
+ X(Br_ge, 13, Br_l, "ge", "jge") \
+ X(Br_le, 14, Br_g, "le", "jle") \
+ X(Br_g, 15, Br_le, "g", "jg")
+//#define X(val, encode, opp, dump, emit)
#define ICEINSTX8664CMPPS_TABLE \
- /* enum value, emit */ \
- X(Cmpps_eq , "eq" ) \
- X(Cmpps_lt , "lt" ) \
- X(Cmpps_le , "le" ) \
+ /* val, emit */ \
+ X(Cmpps_eq, "eq") \
+ X(Cmpps_lt, "lt") \
+ X(Cmpps_le, "le") \
X(Cmpps_unord, "unord") \
- X(Cmpps_neq , "neq" ) \
- X(Cmpps_nlt , "nlt" ) \
- X(Cmpps_nle , "nle" ) \
- X(Cmpps_ord , "ord" )
-//#define X(tag, emit)
+ X(Cmpps_neq, "neq") \
+ X(Cmpps_nlt, "nlt") \
+ X(Cmpps_nle, "nle") \
+ X(Cmpps_ord, "ord")
+//#define X(val, emit)
#define ICETYPEX8664_TABLE \
/* tag , element type, cvt , sdss, pack, width, fld */ \
- X(IceType_void , IceType_void, "?" , "" , "" , "" , "" ) \
- X(IceType_i1 , IceType_void, "si", "" , "" , "b" , "" ) \
- X(IceType_i8 , IceType_void, "si", "" , "" , "b" , "" ) \
- X(IceType_i16 , IceType_void, "si", "" , "" , "w" , "" ) \
- X(IceType_i32 , IceType_void, "si", "" , "" , "l" , "" ) \
- X(IceType_i64 , IceType_void, "si", "" , "" , "q" , "" ) \
- X(IceType_f32 , IceType_void, "ss", "ss", "d" , "" , "s") \
- X(IceType_f64 , IceType_void, "sd", "sd", "q" , "" , "l") \
- X(IceType_v4i1 , IceType_i32 , "?" , "" , "d" , "" , "" ) \
- X(IceType_v8i1 , IceType_i16 , "?" , "" , "w" , "" , "" ) \
- X(IceType_v16i1, IceType_i8 , "?" , "" , "b" , "" , "" ) \
- X(IceType_v16i8, IceType_i8 , "?" , "" , "b" , "" , "" ) \
- X(IceType_v8i16, IceType_i16 , "?" , "" , "w" , "" , "" ) \
- X(IceType_v4i32, IceType_i32 , "dq", "" , "d" , "" , "" ) \
- X(IceType_v4f32, IceType_f32 , "ps", "" , "d" , "" , "" )
+ X(IceType_void, IceType_void, "?", "", "", "", "") \
+ X(IceType_i1, IceType_void, "si", "", "", "b", "") \
+ X(IceType_i8, IceType_void, "si", "", "", "b", "") \
+ X(IceType_i16, IceType_void, "si", "", "", "w", "") \
+ X(IceType_i32, IceType_void, "si", "", "", "l", "") \
+ X(IceType_i64, IceType_void, "si", "", "", "q", "") \
+ X(IceType_f32, IceType_void, "ss", "ss", "d", "", "s") \
+ X(IceType_f64, IceType_void, "sd", "sd", "q", "", "l") \
+ X(IceType_v4i1, IceType_i32, "?", "", "d", "", "") \
+ X(IceType_v8i1, IceType_i16, "?", "", "w", "", "") \
+ X(IceType_v16i1, IceType_i8, "?", "", "b", "", "") \
+ X(IceType_v16i8, IceType_i8, "?", "", "b", "", "") \
+ X(IceType_v8i16, IceType_i16, "?", "", "w", "", "") \
+ X(IceType_v4i32, IceType_i32, "dq", "", "d", "", "") \
+ X(IceType_v4f32, IceType_f32, "ps", "", "d", "", "")
//#define X(tag, elementty, cvt, sdss, pack, width, fld)
#endif // SUBZERO_SRC_ICEINSTX8664_DEF
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