Subzero: Refactor x86 register definitions to use the alias mechanism.

src/IceInstX8664.cpp

Index: src/IceInstX8664.cpp
diff --git a/src/IceInstX8664.cpp b/src/IceInstX8664.cpp
index bf38f1bfd82669508c70421b951fb27ff88a99ec..5c96aeafc37af2841dfcd943e1ee27d551a5e16d 100644
--- a/src/IceInstX8664.cpp
+++ b/src/IceInstX8664.cpp
@@ -32,7 +32,7 @@ namespace X86Internal {
 
 const MachineTraits<TargetX8664>::InstBrAttributesType
     MachineTraits<TargetX8664>::InstBrAttributes[] = {
-#define X(tag, encode, opp, dump, emit)                                        \
+#define X(val, encode, opp, dump, emit)                                        \
   { X8664::Traits::Cond::opp, dump, emit }                                     \
   ,
         ICEINSTX8664BR_TABLE
@@ -41,7 +41,7 @@ const MachineTraits<TargetX8664>::InstBrAttributesType
 
 const MachineTraits<TargetX8664>::InstCmppsAttributesType
     MachineTraits<TargetX8664>::InstCmppsAttributes[] = {
-#define X(tag, emit)                                                           \
+#define X(val, emit)                                                           \
   { emit }                                                                     \
   ,
         ICEINSTX8664CMPPS_TABLE
@@ -96,11 +96,11 @@ void MachineTraits<TargetX8664>::X86OperandMem::emit(const Cfg *Func) const {
   // '$'. Omit the (Base,Index,1<<Shift) part if Base==nullptr.
   if (!Offset) {
     // No offset, emit nothing.
-  } else if (const auto CI = llvm::dyn_cast<ConstantInteger32>(Offset)) {
+  } else if (const auto *CI = llvm::dyn_cast<ConstantInteger32>(Offset)) {
     if (Base == nullptr || CI->getValue())
       // Emit a non-zero offset without a leading '$'.
       Str << CI->getValue();
-  } else if (const auto CR = llvm::dyn_cast<ConstantRelocatable>(Offset)) {
+  } else if (const auto *CR = llvm::dyn_cast<ConstantRelocatable>(Offset)) {
     CR->emitWithoutPrefix(Func->getTarget());
   } else {
     llvm_unreachable("Invalid offset type for x86 mem operand");
@@ -149,7 +149,7 @@ void MachineTraits<TargetX8664>::X86OperandMem::dump(const Cfg *Func,
   bool OffsetIsNegative = false;
   if (!Offset) {
     OffsetIsZero = true;
-  } else if (const auto CI = llvm::dyn_cast<ConstantInteger32>(Offset)) {
+  } else if (const auto *CI = llvm::dyn_cast<ConstantInteger32>(Offset)) {
     OffsetIsZero = (CI->getValue() == 0);
     OffsetIsNegative = (static_cast<int32_t>(CI->getValue()) < 0);
   } else {
@@ -175,7 +175,7 @@ MachineTraits<TargetX8664>::X86OperandMem::toAsmAddress(
   AssemblerFixup *Fixup = nullptr;
   // Determine the offset (is it relocatable?)
   if (getOffset()) {
-    if (const auto CI = llvm::dyn_cast<ConstantInteger32>(getOffset())) {
+    if (const auto *CI = llvm::dyn_cast<ConstantInteger32>(getOffset())) {
       Disp = static_cast<int32_t>(CI->getValue());
     } else if (const auto CR =
                    llvm::dyn_cast<ConstantRelocatable>(getOffset())) {
@@ -188,17 +188,17 @@ MachineTraits<TargetX8664>::X86OperandMem::toAsmAddress(
 
   // Now convert to the various possible forms.
   if (getBase() && getIndex()) {
-    return X8664::Traits::Address(
-        RegX8664::getEncodedGPR(getBase()->getRegNum()),
-        RegX8664::getEncodedGPR(getIndex()->getRegNum()),
-        X8664::Traits::ScaleFactor(getShift()), Disp, Fixup);
+    return X8664::Traits::Address(getEncodedGPR(getBase()->getRegNum()),
+                                  getEncodedGPR(getIndex()->getRegNum()),
+                                  X8664::Traits::ScaleFactor(getShift()), Disp,
+                                  Fixup);
   } else if (getBase()) {
-    return X8664::Traits::Address(
-        RegX8664::getEncodedGPR(getBase()->getRegNum()), Disp, Fixup);
+    return X8664::Traits::Address(getEncodedGPR(getBase()->getRegNum()), Disp,
+                                  Fixup);
   } else if (getIndex()) {
-    return X8664::Traits::Address(
-        RegX8664::getEncodedGPR(getIndex()->getRegNum()),
-        X8664::Traits::ScaleFactor(getShift()), Disp, Fixup);
+    return X8664::Traits::Address(getEncodedGPR(getIndex()->getRegNum()),
+                                  X8664::Traits::ScaleFactor(getShift()), Disp,
+                                  Fixup);
   } else {
     return X8664::Traits::Address(Disp, Fixup);
   }
@@ -210,9 +210,8 @@ MachineTraits<TargetX8664>::VariableSplit::toAsmAddress(const Cfg *Func) const {
   const ::Ice::TargetLowering *Target = Func->getTarget();
   int32_t Offset =
       Var->getStackOffset() + Target->getStackAdjustment() + getOffset();
-  return X8664::Traits::Address(
-      RegX8664::getEncodedGPR(Target->getFrameOrStackReg()), Offset,
-      AssemblerFixup::NoFixup);
+  return X8664::Traits::Address(getEncodedGPR(Target->getFrameOrStackReg()),
+                                Offset, AssemblerFixup::NoFixup);
 }
 
 void MachineTraits<TargetX8664>::VariableSplit::emit(const Cfg *Func) const {
@@ -222,7 +221,7 @@ void MachineTraits<TargetX8664>::VariableSplit::emit(const Cfg *Func) const {
   assert(!Var->hasReg());
   // The following is copied/adapted from TargetX8664::emitVariable().
   const ::Ice::TargetLowering *Target = Func->getTarget();
-  const Type Ty = IceType_i32;
+  constexpr Type Ty = IceType_i32;
   int32_t Offset =
       Var->getStackOffset() + Target->getStackAdjustment() + getOffset();
   if (Offset)