src/trusted/validator_arm/gen/arm32_decode_named_decoder.h - Issue 11569019: Fix uses in ARM table media_instructions.

Unified Diff: src/trusted/validator_arm/gen/arm32_decode_named_decoder.h

Issue 11569019: Fix uses in ARM table media_instructions. (Closed) Base URL: svn://svn.chromium.org/native_client/trunk/src/native_client/

Patch Set: Created 8 years ago

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Index: src/trusted/validator_arm/gen/arm32_decode_named_decoder.h

===================================================================

--- src/trusted/validator_arm/gen/arm32_decode_named_decoder.h (revision 10465)

+++ src/trusted/validator_arm/gen/arm32_decode_named_decoder.h (working copy)

@@ -41,9 +41,9 @@

// by the table methods above. This speeds up the code since

// the class decoders need to only be bulit once (and reused

// for each call to "decode_named").

- const NamedBinary2RegisterBitRangeMsbGeLsb_Bfi_Rule_18_A1_P48 Binary2RegisterBitRangeMsbGeLsb_Bfi_Rule_18_A1_P48_instance_;

- const NamedBinary2RegisterBitRangeNotRnIsPcBitfieldExtract_Sbfx_Rule_154_A1_P308 Binary2RegisterBitRangeNotRnIsPcBitfieldExtract_Sbfx_Rule_154_A1_P308_instance_;

- const NamedBinary2RegisterBitRangeNotRnIsPcBitfieldExtract_Ubfx_Rule_236_A1_P466 Binary2RegisterBitRangeNotRnIsPcBitfieldExtract_Ubfx_Rule_236_A1_P466_instance_;

+ const NamedBinary2RegisterBitRangeMsbGeLsb_BFI Binary2RegisterBitRangeMsbGeLsb_BFI_instance_;

+ const NamedBinary2RegisterBitRangeNotRnIsPcBitfieldExtract_SBFX Binary2RegisterBitRangeNotRnIsPcBitfieldExtract_SBFX_instance_;

+ const NamedBinary2RegisterBitRangeNotRnIsPcBitfieldExtract_UBFX Binary2RegisterBitRangeNotRnIsPcBitfieldExtract_UBFX_instance_;

const NamedBinary2RegisterImmedShiftedTest_CMN_register Binary2RegisterImmedShiftedTest_CMN_register_instance_;

const NamedBinary2RegisterImmedShiftedTest_CMP_register Binary2RegisterImmedShiftedTest_CMP_register_instance_;

const NamedBinary2RegisterImmedShiftedTest_TEQ_register Binary2RegisterImmedShiftedTest_TEQ_register_instance_;

@@ -66,7 +66,7 @@

const NamedBinary3RegisterOpAltA_MUL_A1 Binary3RegisterOpAltA_MUL_A1_instance_;

const NamedBinary3RegisterOpAltA_SMULBB_SMULBT_SMULTB_SMULTT Binary3RegisterOpAltA_SMULBB_SMULBT_SMULTB_SMULTT_instance_;

const NamedBinary3RegisterOpAltA_SMULWB_SMULWT Binary3RegisterOpAltA_SMULWB_SMULWT_instance_;

- const NamedBinary3RegisterOpAltA_Usad8_Rule_253_A1_P500 Binary3RegisterOpAltA_Usad8_Rule_253_A1_P500_instance_;

+ const NamedBinary3RegisterOpAltA_USAD8 Binary3RegisterOpAltA_USAD8_instance_;

const NamedBinary3RegisterOpAltANoCondsUpdate_SDIV Binary3RegisterOpAltANoCondsUpdate_SDIV_instance_;

const NamedBinary3RegisterOpAltANoCondsUpdate_SMMUL Binary3RegisterOpAltANoCondsUpdate_SMMUL_instance_;

const NamedBinary3RegisterOpAltANoCondsUpdate_SMUAD Binary3RegisterOpAltANoCondsUpdate_SMUAD_instance_;

@@ -135,7 +135,7 @@

const NamedBinary4RegisterDualOp_MLS_A1 Binary4RegisterDualOp_MLS_A1_instance_;

const NamedBinary4RegisterDualOp_SMLABB_SMLABT_SMLATB_SMLATT Binary4RegisterDualOp_SMLABB_SMLABT_SMLATB_SMLATT_instance_;

const NamedBinary4RegisterDualOp_SMLAWB_SMLAWT Binary4RegisterDualOp_SMLAWB_SMLAWT_instance_;

- const NamedBinary4RegisterDualOp_Usada8_Rule_254_A1_P502 Binary4RegisterDualOp_Usada8_Rule_254_A1_P502_instance_;

+ const NamedBinary4RegisterDualOp_USADA8 Binary4RegisterDualOp_USADA8_instance_;

const NamedBinary4RegisterDualOpLtV6RdNotRn_MLA_A1 Binary4RegisterDualOpLtV6RdNotRn_MLA_A1_instance_;

const NamedBinary4RegisterDualOpNoCondsUpdate_SMLAD Binary4RegisterDualOpNoCondsUpdate_SMLAD_instance_;

const NamedBinary4RegisterDualOpNoCondsUpdate_SMLSD Binary4RegisterDualOpNoCondsUpdate_SMLSD_instance_;

@@ -281,7 +281,7 @@

const NamedMoveVfpRegisterOp_Vmov_Rule_330_A1_P648 MoveVfpRegisterOp_Vmov_Rule_330_A1_P648_instance_;

const NamedMoveVfpRegisterOpWithTypeSel_Vmov_Rule_328_A1_P644 MoveVfpRegisterOpWithTypeSel_Vmov_Rule_328_A1_P644_instance_;

const NamedMoveVfpRegisterOpWithTypeSel_Vmov_Rule_329_A1_P646 MoveVfpRegisterOpWithTypeSel_Vmov_Rule_329_A1_P646_instance_;

- const NamedPermanentlyUndefined_Udf_Rule_A1 PermanentlyUndefined_Udf_Rule_A1_instance_;

+ const NamedPermanentlyUndefined_UDF PermanentlyUndefined_UDF_instance_;

const NamedPreloadRegisterImm12Op_Pld_Rule_117_A1_P236 PreloadRegisterImm12Op_Pld_Rule_117_A1_P236_instance_;

const NamedPreloadRegisterImm12Op_Pld_Rule_118_A1_P238 PreloadRegisterImm12Op_Pld_Rule_118_A1_P238_instance_;

const NamedPreloadRegisterImm12Op_Pldw_Rule_117_A1_P236 PreloadRegisterImm12Op_Pldw_Rule_117_A1_P236_instance_;

@@ -309,7 +309,7 @@

const NamedStoreVectorRegister_Vstr_Rule_400_A1_A2_P786 StoreVectorRegister_Vstr_Rule_400_A1_A2_P786_instance_;

const NamedStoreVectorRegisterList_Vpush_355_A1_A2_P696 StoreVectorRegisterList_Vpush_355_A1_A2_P696_instance_;

const NamedStoreVectorRegisterList_Vstm_Rule_399_A1_A2_P784 StoreVectorRegisterList_Vstm_Rule_399_A1_A2_P784_instance_;

- const NamedUnary1RegisterBitRangeMsbGeLsb_Bfc_17_A1_P46 Unary1RegisterBitRangeMsbGeLsb_Bfc_17_A1_P46_instance_;

+ const NamedUnary1RegisterBitRangeMsbGeLsb_BFC Unary1RegisterBitRangeMsbGeLsb_BFC_instance_;

const NamedUnary1RegisterImmediateOp12DynCodeReplace_MOV_immediate_A1 Unary1RegisterImmediateOp12DynCodeReplace_MOV_immediate_A1_instance_;

const NamedUnary1RegisterImmediateOp12DynCodeReplace_MVN_immediate Unary1RegisterImmediateOp12DynCodeReplace_MVN_immediate_instance_;

const NamedUnary1RegisterImmediateOpDynCodeReplace_MOVT Unary1RegisterImmediateOpDynCodeReplace_MOVT_instance_;

@@ -512,7 +512,6 @@

const NamedVfpUsesRegOp_Vmsr_Rule_336_A1_P660 VfpUsesRegOp_Vmsr_Rule_336_A1_P660_instance_;

const NamedBranch_B_Rule_16_A1_P44 Branch_B_Rule_16_A1_P44_instance_;

const NamedBranch_Bl_Blx_Rule_23_A1_P58 Branch_Bl_Blx_Rule_23_A1_P58_instance_;

- const NamedDefs12To15CondsDontCareMsbGeLsb_Bfi_Rule_18_A1_P48 Defs12To15CondsDontCareMsbGeLsb_Bfi_Rule_18_A1_P48_instance_;

const NamedDefs12To15CondsDontCareRdRnNotPc_Rbit_Rule_134_A1_P270 Defs12To15CondsDontCareRdRnNotPc_Rbit_Rule_134_A1_P270_instance_;

const NamedDefs12To15CondsDontCareRdRnNotPc_Rev16_Rule_136_A1_P274 Defs12To15CondsDontCareRdRnNotPc_Rev16_Rule_136_A1_P274_instance_;

const NamedDefs12To15CondsDontCareRdRnNotPc_Rev_Rule_135_A1_P272 Defs12To15CondsDontCareRdRnNotPc_Rev_Rule_135_A1_P272_instance_;

@@ -527,8 +526,6 @@

const NamedDefs12To15CondsDontCareRdRnNotPc_Uxtb16_Rule_264_A1_P522 Defs12To15CondsDontCareRdRnNotPc_Uxtb16_Rule_264_A1_P522_instance_;

const NamedDefs12To15CondsDontCareRdRnNotPc_Uxtb_Rule_263_A1_P520 Defs12To15CondsDontCareRdRnNotPc_Uxtb_Rule_263_A1_P520_instance_;

const NamedDefs12To15CondsDontCareRdRnNotPc_Uxth_Rule_265_A1_P524 Defs12To15CondsDontCareRdRnNotPc_Uxth_Rule_265_A1_P524_instance_;

- const NamedDefs12To15CondsDontCareRdRnNotPcBitfieldExtract_Sbfx_Rule_154_A1_P308 Defs12To15CondsDontCareRdRnNotPcBitfieldExtract_Sbfx_Rule_154_A1_P308_instance_;

- const NamedDefs12To15CondsDontCareRdRnNotPcBitfieldExtract_Ubfx_Rule_236_A1_P466 Defs12To15CondsDontCareRdRnNotPcBitfieldExtract_Ubfx_Rule_236_A1_P466_instance_;

const NamedDefs12To15CondsDontCareRnRdRmNotPc_Pkh_Rule_116_A1_P234 Defs12To15CondsDontCareRnRdRmNotPc_Pkh_Rule_116_A1_P234_instance_;

const NamedDefs12To15CondsDontCareRnRdRmNotPc_Qadd16_Rule_125_A1_P252 Defs12To15CondsDontCareRnRdRmNotPc_Qadd16_Rule_125_A1_P252_instance_;

const NamedDefs12To15CondsDontCareRnRdRmNotPc_Qadd8_Rule_126_A1_P254 Defs12To15CondsDontCareRnRdRmNotPc_Qadd8_Rule_126_A1_P254_instance_;

@@ -573,8 +570,6 @@

const NamedDefs12To15CondsDontCareRnRdRmNotPc_Uxtab16_Rule_262_A1_P516 Defs12To15CondsDontCareRnRdRmNotPc_Uxtab16_Rule_262_A1_P516_instance_;

const NamedDefs12To15CondsDontCareRnRdRmNotPc_Uxtab_Rule_260_A1_P514 Defs12To15CondsDontCareRnRdRmNotPc_Uxtab_Rule_260_A1_P514_instance_;

const NamedDefs12To15CondsDontCareRnRdRmNotPc_Uxtah_Rule_262_A1_P518 Defs12To15CondsDontCareRnRdRmNotPc_Uxtah_Rule_262_A1_P518_instance_;

- const NamedDefs16To19CondsDontCareRdRaRmRnNotPc_Usada8_Rule_254_A1_P502 Defs16To19CondsDontCareRdRaRmRnNotPc_Usada8_Rule_254_A1_P502_instance_;

- const NamedDefs16To19CondsDontCareRdRmRnNotPc_Usad8_Rule_253_A1_P500 Defs16To19CondsDontCareRdRmRnNotPc_Usad8_Rule_253_A1_P500_instance_;

const NamedDontCareInst_Msr_Rule_103_A1_P208 DontCareInst_Msr_Rule_103_A1_P208_instance_;

const NamedDontCareInst_Nop_Rule_110_A1_P222 DontCareInst_Nop_Rule_110_A1_P222_instance_;

const NamedDontCareInst_Yield_Rule_413_A1_P812 DontCareInst_Yield_Rule_413_A1_P812_instance_;

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