Fix uses in ARM table media_instructions.

src/trusted/validator_arm/gen/arm32_decode_named_decoder.h

 /*
  * Copyright 2012 The Native Client Authors.  All rights reserved.
  * Use of this source code is governed by a BSD-style license that can
  * be found in the LICENSE file.
  */
 
 // DO NOT EDIT: GENERATED CODE
 
 #ifndef NACL_TRUSTED_BUT_NOT_TCB
 #error This file is not meant for use in the TCB
@@ skipping 23 matching lines @@
   // to use.
   virtual const nacl_arm_dec::ClassDecoder& decode(
      const nacl_arm_dec::Instruction) const;
 
   // The following fields define the set of class decoders
   // that can be returned by the API function "decode_named". They
   // are created once as instance fields, and then returned
   // by the table methods above. This speeds up the code since
   // the class decoders need to only be bulit once (and reused
   // for each call to "decode_named").
-  const NamedBinary2RegisterBitRangeMsbGeLsb_Bfi_Rule_18_A1_P48 Binary2RegisterBitRangeMsbGeLsb_Bfi_Rule_18_A1_P48_instance_;
-  const NamedBinary2RegisterBitRangeNotRnIsPcBitfieldExtract_Sbfx_Rule_154_A1_P308 Binary2RegisterBitRangeNotRnIsPcBitfieldExtract_Sbfx_Rule_154_A1_P308_instance_;
-  const NamedBinary2RegisterBitRangeNotRnIsPcBitfieldExtract_Ubfx_Rule_236_A1_P466 Binary2RegisterBitRangeNotRnIsPcBitfieldExtract_Ubfx_Rule_236_A1_P466_instance_;
+  const NamedBinary2RegisterBitRangeMsbGeLsb_BFI Binary2RegisterBitRangeMsbGeLsb_BFI_instance_;
+  const NamedBinary2RegisterBitRangeNotRnIsPcBitfieldExtract_SBFX Binary2RegisterBitRangeNotRnIsPcBitfieldExtract_SBFX_instance_;
+  const NamedBinary2RegisterBitRangeNotRnIsPcBitfieldExtract_UBFX Binary2RegisterBitRangeNotRnIsPcBitfieldExtract_UBFX_instance_;
   const NamedBinary2RegisterImmedShiftedTest_CMN_register Binary2RegisterImmedShiftedTest_CMN_register_instance_;
   const NamedBinary2RegisterImmedShiftedTest_CMP_register Binary2RegisterImmedShiftedTest_CMP_register_instance_;
   const NamedBinary2RegisterImmedShiftedTest_TEQ_register Binary2RegisterImmedShiftedTest_TEQ_register_instance_;
   const NamedBinary2RegisterImmedShiftedTest_TST_register Binary2RegisterImmedShiftedTest_TST_register_instance_;
   const NamedBinary2RegisterImmediateOp_ADC_immediate Binary2RegisterImmediateOp_ADC_immediate_instance_;
   const NamedBinary2RegisterImmediateOp_AND_immediate Binary2RegisterImmediateOp_AND_immediate_instance_;
   const NamedBinary2RegisterImmediateOp_EOR_immediate Binary2RegisterImmediateOp_EOR_immediate_instance_;
   const NamedBinary2RegisterImmediateOp_RSB_immediate Binary2RegisterImmediateOp_RSB_immediate_instance_;
   const NamedBinary2RegisterImmediateOp_RSC_immediate Binary2RegisterImmediateOp_RSC_immediate_instance_;
   const NamedBinary2RegisterImmediateOp_SBC_immediate Binary2RegisterImmediateOp_SBC_immediate_instance_;
   const NamedBinary2RegisterImmediateOpAddSub_ADD_immediate Binary2RegisterImmediateOpAddSub_ADD_immediate_instance_;
   const NamedBinary2RegisterImmediateOpAddSub_SUB_immediate Binary2RegisterImmediateOpAddSub_SUB_immediate_instance_;
   const NamedBinary2RegisterImmediateOpDynCodeReplace_ORR_immediate Binary2RegisterImmediateOpDynCodeReplace_ORR_immediate_instance_;
   const NamedBinary3RegisterImmedShiftedOpRegsNotPc_Pkh_Rule_116_A1_P234 Binary3RegisterImmedShiftedOpRegsNotPc_Pkh_Rule_116_A1_P234_instance_;
   const NamedBinary3RegisterImmedShiftedOpRegsNotPc_Sxtab16_Rule_221_A1_P436 Binary3RegisterImmedShiftedOpRegsNotPc_Sxtab16_Rule_221_A1_P436_instance_;
   const NamedBinary3RegisterOp_ASR_register Binary3RegisterOp_ASR_register_instance_;
   const NamedBinary3RegisterOp_LSL_register Binary3RegisterOp_LSL_register_instance_;
   const NamedBinary3RegisterOp_LSR_register Binary3RegisterOp_LSR_register_instance_;
   const NamedBinary3RegisterOp_ROR_register Binary3RegisterOp_ROR_register_instance_;
   const NamedBinary3RegisterOpAltA_MUL_A1 Binary3RegisterOpAltA_MUL_A1_instance_;
   const NamedBinary3RegisterOpAltA_SMULBB_SMULBT_SMULTB_SMULTT Binary3RegisterOpAltA_SMULBB_SMULBT_SMULTB_SMULTT_instance_;
   const NamedBinary3RegisterOpAltA_SMULWB_SMULWT Binary3RegisterOpAltA_SMULWB_SMULWT_instance_;
-  const NamedBinary3RegisterOpAltA_Usad8_Rule_253_A1_P500 Binary3RegisterOpAltA_Usad8_Rule_253_A1_P500_instance_;
+  const NamedBinary3RegisterOpAltA_USAD8 Binary3RegisterOpAltA_USAD8_instance_;
   const NamedBinary3RegisterOpAltANoCondsUpdate_SDIV Binary3RegisterOpAltANoCondsUpdate_SDIV_instance_;
   const NamedBinary3RegisterOpAltANoCondsUpdate_SMMUL Binary3RegisterOpAltANoCondsUpdate_SMMUL_instance_;
   const NamedBinary3RegisterOpAltANoCondsUpdate_SMUAD Binary3RegisterOpAltANoCondsUpdate_SMUAD_instance_;
   const NamedBinary3RegisterOpAltANoCondsUpdate_SMUSD Binary3RegisterOpAltANoCondsUpdate_SMUSD_instance_;
   const NamedBinary3RegisterOpAltANoCondsUpdate_UDIV Binary3RegisterOpAltANoCondsUpdate_UDIV_instance_;
   const NamedBinary3RegisterOpAltBNoCondUpdates_QADD Binary3RegisterOpAltBNoCondUpdates_QADD_instance_;
   const NamedBinary3RegisterOpAltBNoCondUpdates_QDADD Binary3RegisterOpAltBNoCondUpdates_QDADD_instance_;
   const NamedBinary3RegisterOpAltBNoCondUpdates_QDSUB Binary3RegisterOpAltBNoCondUpdates_QDSUB_instance_;
   const NamedBinary3RegisterOpAltBNoCondUpdates_QSUB Binary3RegisterOpAltBNoCondUpdates_QSUB_instance_;
   const NamedBinary3RegisterOpAltBNoCondUpdates_Qadd16_Rule_125_A1_P252 Binary3RegisterOpAltBNoCondUpdates_Qadd16_Rule_125_A1_P252_instance_;
@@ skipping 48 matching lines @@
   const NamedBinary3RegisterShiftedOp_RSC_register Binary3RegisterShiftedOp_RSC_register_instance_;
   const NamedBinary3RegisterShiftedOp_SBC_register Binary3RegisterShiftedOp_SBC_register_instance_;
   const NamedBinary3RegisterShiftedOp_SUB_register Binary3RegisterShiftedOp_SUB_register_instance_;
   const NamedBinary3RegisterShiftedTest_CMN_register_shifted_register Binary3RegisterShiftedTest_CMN_register_shifted_register_instance_;
   const NamedBinary3RegisterShiftedTest_CMP_register_shifted_register Binary3RegisterShiftedTest_CMP_register_shifted_register_instance_;
   const NamedBinary3RegisterShiftedTest_TEQ_register_shifted_register Binary3RegisterShiftedTest_TEQ_register_shifted_register_instance_;
   const NamedBinary3RegisterShiftedTest_TST_register_shifted_register Binary3RegisterShiftedTest_TST_register_shifted_register_instance_;
   const NamedBinary4RegisterDualOp_MLS_A1 Binary4RegisterDualOp_MLS_A1_instance_;
   const NamedBinary4RegisterDualOp_SMLABB_SMLABT_SMLATB_SMLATT Binary4RegisterDualOp_SMLABB_SMLABT_SMLATB_SMLATT_instance_;
   const NamedBinary4RegisterDualOp_SMLAWB_SMLAWT Binary4RegisterDualOp_SMLAWB_SMLAWT_instance_;
-  const NamedBinary4RegisterDualOp_Usada8_Rule_254_A1_P502 Binary4RegisterDualOp_Usada8_Rule_254_A1_P502_instance_;
+  const NamedBinary4RegisterDualOp_USADA8 Binary4RegisterDualOp_USADA8_instance_;
   const NamedBinary4RegisterDualOpLtV6RdNotRn_MLA_A1 Binary4RegisterDualOpLtV6RdNotRn_MLA_A1_instance_;
   const NamedBinary4RegisterDualOpNoCondsUpdate_SMLAD Binary4RegisterDualOpNoCondsUpdate_SMLAD_instance_;
   const NamedBinary4RegisterDualOpNoCondsUpdate_SMLSD Binary4RegisterDualOpNoCondsUpdate_SMLSD_instance_;
   const NamedBinary4RegisterDualOpNoCondsUpdate_SMMLA Binary4RegisterDualOpNoCondsUpdate_SMMLA_instance_;
   const NamedBinary4RegisterDualOpNoCondsUpdate_SMMLS Binary4RegisterDualOpNoCondsUpdate_SMMLS_instance_;
   const NamedBinary4RegisterDualResult_SMLALBB_SMLALBT_SMLALTB_SMLALTT Binary4RegisterDualResult_SMLALBB_SMLALBT_SMLALTB_SMLALTT_instance_;
   const NamedBinary4RegisterDualResult_UMAAL_A1 Binary4RegisterDualResult_UMAAL_A1_instance_;
   const NamedBinary4RegisterDualResultLtV6RdHiLoNotRn_SMLAL_A1 Binary4RegisterDualResultLtV6RdHiLoNotRn_SMLAL_A1_instance_;
   const NamedBinary4RegisterDualResultLtV6RdHiLoNotRn_UMLAL_A1 Binary4RegisterDualResultLtV6RdHiLoNotRn_UMLAL_A1_instance_;
   const NamedBinary4RegisterDualResultNoCondsUpdate_SMLALD Binary4RegisterDualResultNoCondsUpdate_SMLALD_instance_;
@@ skipping 125 matching lines @@
   const NamedLoadVectorRegisterList_Vldm_Rule_319_A1_A2_P626 LoadVectorRegisterList_Vldm_Rule_319_A1_A2_P626_instance_;
   const NamedLoadVectorRegisterList_Vpop_Rule_354_A1_A2_P694 LoadVectorRegisterList_Vpop_Rule_354_A1_A2_P694_instance_;
   const NamedMaskedBinary2RegisterImmediateOp_BIC_immediate MaskedBinary2RegisterImmediateOp_BIC_immediate_instance_;
   const NamedMaskedBinaryRegisterImmediateTest_TST_immediate MaskedBinaryRegisterImmediateTest_TST_immediate_instance_;
   const NamedMoveDoubleVfpRegisterOp_Vmov_one_D_Rule_A1 MoveDoubleVfpRegisterOp_Vmov_one_D_Rule_A1_instance_;
   const NamedMoveDoubleVfpRegisterOp_Vmov_two_S_Rule_A1 MoveDoubleVfpRegisterOp_Vmov_two_S_Rule_A1_instance_;
   const NamedMoveImmediate12ToApsr_Msr_Rule_103_A1_P208 MoveImmediate12ToApsr_Msr_Rule_103_A1_P208_instance_;
   const NamedMoveVfpRegisterOp_Vmov_Rule_330_A1_P648 MoveVfpRegisterOp_Vmov_Rule_330_A1_P648_instance_;
   const NamedMoveVfpRegisterOpWithTypeSel_Vmov_Rule_328_A1_P644 MoveVfpRegisterOpWithTypeSel_Vmov_Rule_328_A1_P644_instance_;
   const NamedMoveVfpRegisterOpWithTypeSel_Vmov_Rule_329_A1_P646 MoveVfpRegisterOpWithTypeSel_Vmov_Rule_329_A1_P646_instance_;
-  const NamedPermanentlyUndefined_Udf_Rule_A1 PermanentlyUndefined_Udf_Rule_A1_instance_;
+  const NamedPermanentlyUndefined_UDF PermanentlyUndefined_UDF_instance_;
   const NamedPreloadRegisterImm12Op_Pld_Rule_117_A1_P236 PreloadRegisterImm12Op_Pld_Rule_117_A1_P236_instance_;
   const NamedPreloadRegisterImm12Op_Pld_Rule_118_A1_P238 PreloadRegisterImm12Op_Pld_Rule_118_A1_P238_instance_;
   const NamedPreloadRegisterImm12Op_Pldw_Rule_117_A1_P236 PreloadRegisterImm12Op_Pldw_Rule_117_A1_P236_instance_;
   const NamedPreloadRegisterImm12Op_Pli_Rule_120_A1_P242 PreloadRegisterImm12Op_Pli_Rule_120_A1_P242_instance_;
   const NamedPreloadRegisterPairOp_Pld_Rule_119_A1_P240 PreloadRegisterPairOp_Pld_Rule_119_A1_P240_instance_;
   const NamedPreloadRegisterPairOp_Pldw_Rule_119_A1_P240 PreloadRegisterPairOp_Pldw_Rule_119_A1_P240_instance_;
   const NamedPreloadRegisterPairOp_Pli_Rule_121_A1_P244 PreloadRegisterPairOp_Pli_Rule_121_A1_P244_instance_;
   const NamedStore2RegisterImm12Op_STRB_immediate Store2RegisterImm12Op_STRB_immediate_instance_;
   const NamedStore2RegisterImm12Op_STR_immediate Store2RegisterImm12Op_STR_immediate_instance_;
   const NamedStore2RegisterImm8DoubleOp_STRD_immediate Store2RegisterImm8DoubleOp_STRD_immediate_instance_;
   const NamedStore2RegisterImm8Op_STRH_immediate Store2RegisterImm8Op_STRH_immediate_instance_;
   const NamedStore3RegisterDoubleOp_STRD_register Store3RegisterDoubleOp_STRD_register_instance_;
   const NamedStore3RegisterImm5Op_STRB_register Store3RegisterImm5Op_STRB_register_instance_;
   const NamedStore3RegisterImm5Op_STR_register Store3RegisterImm5Op_STR_register_instance_;
   const NamedStore3RegisterOp_STRH_register Store3RegisterOp_STRH_register_instance_;
   const NamedStoreExclusive3RegisterDoubleOp_STREXD StoreExclusive3RegisterDoubleOp_STREXD_instance_;
   const NamedStoreExclusive3RegisterOp_STREX StoreExclusive3RegisterOp_STREX_instance_;
   const NamedStoreExclusive3RegisterOp_STREXB StoreExclusive3RegisterOp_STREXB_instance_;
   const NamedStoreExclusive3RegisterOp_STREXH StoreExclusive3RegisterOp_STREXH_instance_;
   const NamedStoreRegisterList_Push_Rule_A1 StoreRegisterList_Push_Rule_A1_instance_;
   const NamedStoreRegisterList_Stm_Stmia_Stmea_Rule_189_A1_P374 StoreRegisterList_Stm_Stmia_Stmea_Rule_189_A1_P374_instance_;
   const NamedStoreRegisterList_Stmda_Stmed_Rule_190_A1_P376 StoreRegisterList_Stmda_Stmed_Rule_190_A1_P376_instance_;
   const NamedStoreRegisterList_Stmdb_Stmfd_Rule_191_A1_P378 StoreRegisterList_Stmdb_Stmfd_Rule_191_A1_P378_instance_;
   const NamedStoreRegisterList_Stmib_Stmfa_Rule_192_A1_P380 StoreRegisterList_Stmib_Stmfa_Rule_192_A1_P380_instance_;
   const NamedStoreVectorRegister_Vstr_Rule_400_A1_A2_P786 StoreVectorRegister_Vstr_Rule_400_A1_A2_P786_instance_;
   const NamedStoreVectorRegisterList_Vpush_355_A1_A2_P696 StoreVectorRegisterList_Vpush_355_A1_A2_P696_instance_;
   const NamedStoreVectorRegisterList_Vstm_Rule_399_A1_A2_P784 StoreVectorRegisterList_Vstm_Rule_399_A1_A2_P784_instance_;
-  const NamedUnary1RegisterBitRangeMsbGeLsb_Bfc_17_A1_P46 Unary1RegisterBitRangeMsbGeLsb_Bfc_17_A1_P46_instance_;
+  const NamedUnary1RegisterBitRangeMsbGeLsb_BFC Unary1RegisterBitRangeMsbGeLsb_BFC_instance_;
   const NamedUnary1RegisterImmediateOp12DynCodeReplace_MOV_immediate_A1 Unary1RegisterImmediateOp12DynCodeReplace_MOV_immediate_A1_instance_;
   const NamedUnary1RegisterImmediateOp12DynCodeReplace_MVN_immediate Unary1RegisterImmediateOp12DynCodeReplace_MVN_immediate_instance_;
   const NamedUnary1RegisterImmediateOpDynCodeReplace_MOVT Unary1RegisterImmediateOpDynCodeReplace_MOVT_instance_;
   const NamedUnary1RegisterImmediateOpDynCodeReplace_MOVW Unary1RegisterImmediateOpDynCodeReplace_MOVW_instance_;
   const NamedUnary1RegisterImmediateOpPc_ADR_A1 Unary1RegisterImmediateOpPc_ADR_A1_instance_;
   const NamedUnary1RegisterImmediateOpPc_ADR_A2 Unary1RegisterImmediateOpPc_ADR_A2_instance_;
   const NamedUnary1RegisterSet_MRS Unary1RegisterSet_MRS_instance_;
   const NamedUnary1RegisterUse_MSR_register Unary1RegisterUse_MSR_register_instance_;
   const NamedUnary2RegisterImmedShiftedOpRegsNotPc_Sxtb16_Rule_224_A1_P442 Unary2RegisterImmedShiftedOpRegsNotPc_Sxtb16_Rule_224_A1_P442_instance_;
   const NamedUnary2RegisterImmedShiftedOpRegsNotPc_Sxtb_Rule_223_A1_P440 Unary2RegisterImmedShiftedOpRegsNotPc_Sxtb_Rule_223_A1_P440_instance_;
@@ skipping 182 matching lines @@
   const NamedVectorLoadStoreSingle2_VST2_single_2_element_structure_from_one_lane VectorLoadStoreSingle2_VST2_single_2_element_structure_from_one_lane_instance_;
   const NamedVectorLoadStoreSingle3_VLD3_single_3_element_structure_to_one_lane VectorLoadStoreSingle3_VLD3_single_3_element_structure_to_one_lane_instance_;
   const NamedVectorLoadStoreSingle3_VST3_single_3_element_structure_from_one_lane VectorLoadStoreSingle3_VST3_single_3_element_structure_from_one_lane_instance_;
   const NamedVectorLoadStoreSingle4_VLD4_single_4_element_structure_to_one_lane VectorLoadStoreSingle4_VLD4_single_4_element_structure_to_one_lane_instance_;
   const NamedVectorLoadStoreSingle4_VST4_single_4_element_structure_form_one_lane VectorLoadStoreSingle4_VST4_single_4_element_structure_form_one_lane_instance_;
   const NamedVectorUnary2RegisterDup_Vdup_Rule_302_A1_P592 VectorUnary2RegisterDup_Vdup_Rule_302_A1_P592_instance_;
   const NamedVfpMrsOp_Vmrs_Rule_335_A1_P658 VfpMrsOp_Vmrs_Rule_335_A1_P658_instance_;
   const NamedVfpUsesRegOp_Vmsr_Rule_336_A1_P660 VfpUsesRegOp_Vmsr_Rule_336_A1_P660_instance_;
   const NamedBranch_B_Rule_16_A1_P44 Branch_B_Rule_16_A1_P44_instance_;
   const NamedBranch_Bl_Blx_Rule_23_A1_P58 Branch_Bl_Blx_Rule_23_A1_P58_instance_;
-  const NamedDefs12To15CondsDontCareMsbGeLsb_Bfi_Rule_18_A1_P48 Defs12To15CondsDontCareMsbGeLsb_Bfi_Rule_18_A1_P48_instance_;
   const NamedDefs12To15CondsDontCareRdRnNotPc_Rbit_Rule_134_A1_P270 Defs12To15CondsDontCareRdRnNotPc_Rbit_Rule_134_A1_P270_instance_;
   const NamedDefs12To15CondsDontCareRdRnNotPc_Rev16_Rule_136_A1_P274 Defs12To15CondsDontCareRdRnNotPc_Rev16_Rule_136_A1_P274_instance_;
   const NamedDefs12To15CondsDontCareRdRnNotPc_Rev_Rule_135_A1_P272 Defs12To15CondsDontCareRdRnNotPc_Rev_Rule_135_A1_P272_instance_;
   const NamedDefs12To15CondsDontCareRdRnNotPc_Revsh_Rule_137_A1_P276 Defs12To15CondsDontCareRdRnNotPc_Revsh_Rule_137_A1_P276_instance_;
   const NamedDefs12To15CondsDontCareRdRnNotPc_Ssat16_Rule_184_A1_P364 Defs12To15CondsDontCareRdRnNotPc_Ssat16_Rule_184_A1_P364_instance_;
   const NamedDefs12To15CondsDontCareRdRnNotPc_Ssat_Rule_183_A1_P362 Defs12To15CondsDontCareRdRnNotPc_Ssat_Rule_183_A1_P362_instance_;
   const NamedDefs12To15CondsDontCareRdRnNotPc_Sxtb16_Rule_224_A1_P442 Defs12To15CondsDontCareRdRnNotPc_Sxtb16_Rule_224_A1_P442_instance_;
   const NamedDefs12To15CondsDontCareRdRnNotPc_Sxtb_Rule_223_A1_P440 Defs12To15CondsDontCareRdRnNotPc_Sxtb_Rule_223_A1_P440_instance_;
   const NamedDefs12To15CondsDontCareRdRnNotPc_Sxth_Rule_225_A1_P444 Defs12To15CondsDontCareRdRnNotPc_Sxth_Rule_225_A1_P444_instance_;
   const NamedDefs12To15CondsDontCareRdRnNotPc_Usat16_Rule_256_A1_P506 Defs12To15CondsDontCareRdRnNotPc_Usat16_Rule_256_A1_P506_instance_;
   const NamedDefs12To15CondsDontCareRdRnNotPc_Usat_Rule_255_A1_P504 Defs12To15CondsDontCareRdRnNotPc_Usat_Rule_255_A1_P504_instance_;
   const NamedDefs12To15CondsDontCareRdRnNotPc_Uxtb16_Rule_264_A1_P522 Defs12To15CondsDontCareRdRnNotPc_Uxtb16_Rule_264_A1_P522_instance_;
   const NamedDefs12To15CondsDontCareRdRnNotPc_Uxtb_Rule_263_A1_P520 Defs12To15CondsDontCareRdRnNotPc_Uxtb_Rule_263_A1_P520_instance_;
   const NamedDefs12To15CondsDontCareRdRnNotPc_Uxth_Rule_265_A1_P524 Defs12To15CondsDontCareRdRnNotPc_Uxth_Rule_265_A1_P524_instance_;
-  const NamedDefs12To15CondsDontCareRdRnNotPcBitfieldExtract_Sbfx_Rule_154_A1_P308 Defs12To15CondsDontCareRdRnNotPcBitfieldExtract_Sbfx_Rule_154_A1_P308_instance_;
-  const NamedDefs12To15CondsDontCareRdRnNotPcBitfieldExtract_Ubfx_Rule_236_A1_P466 Defs12To15CondsDontCareRdRnNotPcBitfieldExtract_Ubfx_Rule_236_A1_P466_instance_;
   const NamedDefs12To15CondsDontCareRnRdRmNotPc_Pkh_Rule_116_A1_P234 Defs12To15CondsDontCareRnRdRmNotPc_Pkh_Rule_116_A1_P234_instance_;
   const NamedDefs12To15CondsDontCareRnRdRmNotPc_Qadd16_Rule_125_A1_P252 Defs12To15CondsDontCareRnRdRmNotPc_Qadd16_Rule_125_A1_P252_instance_;
   const NamedDefs12To15CondsDontCareRnRdRmNotPc_Qadd8_Rule_126_A1_P254 Defs12To15CondsDontCareRnRdRmNotPc_Qadd8_Rule_126_A1_P254_instance_;
   const NamedDefs12To15CondsDontCareRnRdRmNotPc_Qasx_Rule_127_A1_P256 Defs12To15CondsDontCareRnRdRmNotPc_Qasx_Rule_127_A1_P256_instance_;
   const NamedDefs12To15CondsDontCareRnRdRmNotPc_Qsax_Rule_130_A1_P262 Defs12To15CondsDontCareRnRdRmNotPc_Qsax_Rule_130_A1_P262_instance_;
   const NamedDefs12To15CondsDontCareRnRdRmNotPc_Qsub16_Rule_132_A1_P266 Defs12To15CondsDontCareRnRdRmNotPc_Qsub16_Rule_132_A1_P266_instance_;
   const NamedDefs12To15CondsDontCareRnRdRmNotPc_Qsub8_Rule_133_A1_P268 Defs12To15CondsDontCareRnRdRmNotPc_Qsub8_Rule_133_A1_P268_instance_;
   const NamedDefs12To15CondsDontCareRnRdRmNotPc_Sadd16_Rule_148_A1_P296 Defs12To15CondsDontCareRnRdRmNotPc_Sadd16_Rule_148_A1_P296_instance_;
   const NamedDefs12To15CondsDontCareRnRdRmNotPc_Sadd8_Rule_149_A1_P298 Defs12To15CondsDontCareRnRdRmNotPc_Sadd8_Rule_149_A1_P298_instance_;
   const NamedDefs12To15CondsDontCareRnRdRmNotPc_Sasx_Rule_150_A1_P300 Defs12To15CondsDontCareRnRdRmNotPc_Sasx_Rule_150_A1_P300_instance_;
@@ skipping 24 matching lines @@
   const NamedDefs12To15CondsDontCareRnRdRmNotPc_Uqasx_Rule_249_A1_P492 Defs12To15CondsDontCareRnRdRmNotPc_Uqasx_Rule_249_A1_P492_instance_;
   const NamedDefs12To15CondsDontCareRnRdRmNotPc_Uqsax_Rule_250_A1_P494 Defs12To15CondsDontCareRnRdRmNotPc_Uqsax_Rule_250_A1_P494_instance_;
   const NamedDefs12To15CondsDontCareRnRdRmNotPc_Uqsub16_Rule_251_A1_P496 Defs12To15CondsDontCareRnRdRmNotPc_Uqsub16_Rule_251_A1_P496_instance_;
   const NamedDefs12To15CondsDontCareRnRdRmNotPc_Uqsub8_Rule_252_A1_P498 Defs12To15CondsDontCareRnRdRmNotPc_Uqsub8_Rule_252_A1_P498_instance_;
   const NamedDefs12To15CondsDontCareRnRdRmNotPc_Usax_Rule_257_A1_P508 Defs12To15CondsDontCareRnRdRmNotPc_Usax_Rule_257_A1_P508_instance_;
   const NamedDefs12To15CondsDontCareRnRdRmNotPc_Usub16_Rule_258_A1_P510 Defs12To15CondsDontCareRnRdRmNotPc_Usub16_Rule_258_A1_P510_instance_;
   const NamedDefs12To15CondsDontCareRnRdRmNotPc_Usub8_Rule_259_A1_P512 Defs12To15CondsDontCareRnRdRmNotPc_Usub8_Rule_259_A1_P512_instance_;
   const NamedDefs12To15CondsDontCareRnRdRmNotPc_Uxtab16_Rule_262_A1_P516 Defs12To15CondsDontCareRnRdRmNotPc_Uxtab16_Rule_262_A1_P516_instance_;
   const NamedDefs12To15CondsDontCareRnRdRmNotPc_Uxtab_Rule_260_A1_P514 Defs12To15CondsDontCareRnRdRmNotPc_Uxtab_Rule_260_A1_P514_instance_;
   const NamedDefs12To15CondsDontCareRnRdRmNotPc_Uxtah_Rule_262_A1_P518 Defs12To15CondsDontCareRnRdRmNotPc_Uxtah_Rule_262_A1_P518_instance_;
-  const NamedDefs16To19CondsDontCareRdRaRmRnNotPc_Usada8_Rule_254_A1_P502 Defs16To19CondsDontCareRdRaRmRnNotPc_Usada8_Rule_254_A1_P502_instance_;
-  const NamedDefs16To19CondsDontCareRdRmRnNotPc_Usad8_Rule_253_A1_P500 Defs16To19CondsDontCareRdRmRnNotPc_Usad8_Rule_253_A1_P500_instance_;
   const NamedDontCareInst_Msr_Rule_103_A1_P208 DontCareInst_Msr_Rule_103_A1_P208_instance_;
   const NamedDontCareInst_Nop_Rule_110_A1_P222 DontCareInst_Nop_Rule_110_A1_P222_instance_;
   const NamedDontCareInst_Yield_Rule_413_A1_P812 DontCareInst_Yield_Rule_413_A1_P812_instance_;
   const NamedDontCareInstRdNotPc_Vmsr_Rule_336_A1_P660 DontCareInstRdNotPc_Vmsr_Rule_336_A1_P660_instance_;
   const NamedForbidden_BXJ Forbidden_BXJ_instance_;
   const NamedForbidden_Blx_Rule_23_A2_P58 Forbidden_Blx_Rule_23_A2_P58_instance_;
   const NamedForbidden_Cdp2_Rule_28_A2_P68 Forbidden_Cdp2_Rule_28_A2_P68_instance_;
   const NamedForbidden_Cdp_Rule_A1 Forbidden_Cdp_Rule_A1_instance_;
   const NamedForbidden_Clrex_Rule_30_A1_P70 Forbidden_Clrex_Rule_30_A1_P70_instance_;
   const NamedForbidden_Cps_Rule_b6_1_1_A1_B6_3 Forbidden_Cps_Rule_b6_1_1_A1_B6_3_instance_;
@@ skipping 136 matching lines @@
       const nacl_arm_dec::Instruction inst) const;
   inline const NamedClassDecoder& decode_unconditional_instructions(
       const nacl_arm_dec::Instruction inst) const;
   // Defines default action if parse tables don't define what action
   // to take.
   const NotImplementedNamed not_implemented_;
 };
 
 } // namespace nacl_arm_test
 #endif  // NATIVE_CLIENT_SRC_TRUSTED_VALIDATOR_ARM_GEN_ARM32_DECODE_NAMED_DECODER_H_