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1 // Copyright 2012 the V8 project authors. All rights reserved. | 1 // Copyright 2012 the V8 project authors. All rights reserved. |
2 // Redistribution and use in source and binary forms, with or without | 2 // Redistribution and use in source and binary forms, with or without |
3 // modification, are permitted provided that the following conditions are | 3 // modification, are permitted provided that the following conditions are |
4 // met: | 4 // met: |
5 // | 5 // |
6 // * Redistributions of source code must retain the above copyright | 6 // * Redistributions of source code must retain the above copyright |
7 // notice, this list of conditions and the following disclaimer. | 7 // notice, this list of conditions and the following disclaimer. |
8 // * Redistributions in binary form must reproduce the above | 8 // * Redistributions in binary form must reproduce the above |
9 // copyright notice, this list of conditions and the following | 9 // copyright notice, this list of conditions and the following |
10 // disclaimer in the documentation and/or other materials provided | 10 // disclaimer in the documentation and/or other materials provided |
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1979 // the destination for the operation, but it confusingly uses the | 1979 // the destination for the operation, but it confusingly uses the |
1980 // Rn field to encode it. | 1980 // Rn field to encode it. |
1981 // Format(instr, "mul'cond's 'rn, 'rm, 'rs"); | 1981 // Format(instr, "mul'cond's 'rn, 'rm, 'rs"); |
1982 int rd = rn; // Remap the rn field to the Rd register. | 1982 int rd = rn; // Remap the rn field to the Rd register. |
1983 int32_t alu_out = rm_val * rs_val; | 1983 int32_t alu_out = rm_val * rs_val; |
1984 set_register(rd, alu_out); | 1984 set_register(rd, alu_out); |
1985 if (instr->HasS()) { | 1985 if (instr->HasS()) { |
1986 SetNZFlags(alu_out); | 1986 SetNZFlags(alu_out); |
1987 } | 1987 } |
1988 } else { | 1988 } else { |
1989 int rd = instr->RdValue(); | 1989 // The MLA instruction description (A 4.1.28) refers to the order |
1990 int32_t acc_value = get_register(rd); | 1990 // of registers as "Rd, Rm, Rs, Rn". But confusingly it uses the |
1991 if (instr->Bit(22) == 0) { | 1991 // Rn field to encode the Rd register and the Rd field to encode |
1992 // The MLA instruction description (A 4.1.28) refers to the order | 1992 // the Rn register. |
1993 // of registers as "Rd, Rm, Rs, Rn". But confusingly it uses the | 1993 Format(instr, "mla'cond's 'rn, 'rm, 'rs, 'rd"); |
1994 // Rn field to encode the Rd register and the Rd field to encode | |
1995 // the Rn register. | |
1996 // Format(instr, "mla'cond's 'rn, 'rm, 'rs, 'rd"); | |
1997 int32_t mul_out = rm_val * rs_val; | |
1998 int32_t result = acc_value + mul_out; | |
1999 set_register(rn, result); | |
2000 } else { | |
2001 // Format(instr, "mls'cond's 'rn, 'rm, 'rs, 'rd"); | |
2002 int32_t mul_out = rm_val * rs_val; | |
2003 int32_t result = acc_value - mul_out; | |
2004 set_register(rn, result); | |
2005 } | |
2006 } | 1994 } |
2007 } else { | 1995 } else { |
2008 // The signed/long multiply instructions use the terms RdHi and RdLo | 1996 // The signed/long multiply instructions use the terms RdHi and RdLo |
2009 // when referring to the target registers. They are mapped to the Rn | 1997 // when referring to the target registers. They are mapped to the Rn |
2010 // and Rd fields as follows: | 1998 // and Rd fields as follows: |
2011 // RdLo == Rd | 1999 // RdLo == Rd |
2012 // RdHi == Rn (This is confusingly stored in variable rd here | 2000 // RdHi == Rn (This is confusingly stored in variable rd here |
2013 // because the mul instruction from above uses the | 2001 // because the mul instruction from above uses the |
2014 // Rn field to encode the Rd register. Good luck figuring | 2002 // Rn field to encode the Rd register. Good luck figuring |
2015 // this out without reading the ARM instruction manual | 2003 // this out without reading the ARM instruction manual |
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2551 UNIMPLEMENTED(); | 2539 UNIMPLEMENTED(); |
2552 } | 2540 } |
2553 return; | 2541 return; |
2554 } else { | 2542 } else { |
2555 Format(instr, "'memop'cond'b 'rd, ['rn], +'shift_rm"); | 2543 Format(instr, "'memop'cond'b 'rd, ['rn], +'shift_rm"); |
2556 UNIMPLEMENTED(); | 2544 UNIMPLEMENTED(); |
2557 } | 2545 } |
2558 break; | 2546 break; |
2559 } | 2547 } |
2560 case db_x: { | 2548 case db_x: { |
2561 if (FLAG_enable_sudiv) { | |
2562 if (!instr->HasW()) { | |
2563 if (instr->Bits(5, 4) == 0x1) { | |
2564 if ((instr->Bit(22) == 0x0) && (instr->Bit(20) == 0x1)) { | |
2565 // sdiv (in V8 notation matching ARM ISA format) rn = rm/rs | |
2566 // Format(instr, "'sdiv'cond'b 'rn, 'rm, 'rs); | |
2567 int rm = instr->RmValue(); | |
2568 int32_t rm_val = get_register(rm); | |
2569 int rs = instr->RsValue(); | |
2570 int32_t rs_val = get_register(rs); | |
2571 int32_t ret_val = 0; | |
2572 ASSERT(rs_val != 0); | |
2573 ret_val = rm_val/rs_val; | |
2574 set_register(rn, ret_val); | |
2575 return; | |
2576 } | |
2577 } | |
2578 } | |
2579 } | |
2580 // Format(instr, "'memop'cond'b 'rd, ['rn, -'shift_rm]'w"); | 2549 // Format(instr, "'memop'cond'b 'rd, ['rn, -'shift_rm]'w"); |
2581 addr = rn_val - shifter_operand; | 2550 addr = rn_val - shifter_operand; |
2582 if (instr->HasW()) { | 2551 if (instr->HasW()) { |
2583 set_register(rn, addr); | 2552 set_register(rn, addr); |
2584 } | 2553 } |
2585 break; | 2554 break; |
2586 } | 2555 } |
2587 case ib_x: { | 2556 case ib_x: { |
2588 if (instr->HasW() && (instr->Bits(6, 4) == 0x5)) { | 2557 if (instr->HasW() && (instr->Bits(6, 4) == 0x5)) { |
2589 uint32_t widthminus1 = static_cast<uint32_t>(instr->Bits(20, 16)); | 2558 uint32_t widthminus1 = static_cast<uint32_t>(instr->Bits(20, 16)); |
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3415 uintptr_t address = *stack_slot; | 3384 uintptr_t address = *stack_slot; |
3416 set_register(sp, current_sp + sizeof(uintptr_t)); | 3385 set_register(sp, current_sp + sizeof(uintptr_t)); |
3417 return address; | 3386 return address; |
3418 } | 3387 } |
3419 | 3388 |
3420 } } // namespace v8::internal | 3389 } } // namespace v8::internal |
3421 | 3390 |
3422 #endif // USE_SIMULATOR | 3391 #endif // USE_SIMULATOR |
3423 | 3392 |
3424 #endif // V8_TARGET_ARCH_ARM | 3393 #endif // V8_TARGET_ARCH_ARM |
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