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1 // Copyright (c) 1994-2006 Sun Microsystems Inc. | 1 // Copyright (c) 1994-2006 Sun Microsystems Inc. |
2 // All Rights Reserved. | 2 // All Rights Reserved. |
3 // | 3 // |
4 // Redistribution and use in source and binary forms, with or without | 4 // Redistribution and use in source and binary forms, with or without |
5 // modification, are permitted provided that the following conditions | 5 // modification, are permitted provided that the following conditions |
6 // are met: | 6 // are met: |
7 // | 7 // |
8 // - Redistributions of source code must retain the above copyright notice, | 8 // - Redistributions of source code must retain the above copyright notice, |
9 // this list of conditions and the following disclaimer. | 9 // this list of conditions and the following disclaimer. |
10 // | 10 // |
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103 #ifndef __arm__ | 103 #ifndef __arm__ |
104 // For the simulator=arm build, use VFP when FLAG_enable_vfp3 is | 104 // For the simulator=arm build, use VFP when FLAG_enable_vfp3 is |
105 // enabled. VFPv3 implies ARMv7, see ARM DDI 0406B, page A1-6. | 105 // enabled. VFPv3 implies ARMv7, see ARM DDI 0406B, page A1-6. |
106 if (FLAG_enable_vfp3) { | 106 if (FLAG_enable_vfp3) { |
107 supported_ |= 1u << VFP3 | 1u << ARMv7 | 1u << VFP2; | 107 supported_ |= 1u << VFP3 | 1u << ARMv7 | 1u << VFP2; |
108 } | 108 } |
109 // For the simulator=arm build, use ARMv7 when FLAG_enable_armv7 is enabled | 109 // For the simulator=arm build, use ARMv7 when FLAG_enable_armv7 is enabled |
110 if (FLAG_enable_armv7) { | 110 if (FLAG_enable_armv7) { |
111 supported_ |= 1u << ARMv7; | 111 supported_ |= 1u << ARMv7; |
112 } | 112 } |
113 | |
114 if (FLAG_enable_sudiv) { | |
115 supported_ |= 1u << SUDIV; | |
116 } | |
117 #else // __arm__ | 113 #else // __arm__ |
118 // Probe for additional features not already known to be available. | 114 // Probe for additional features not already known to be available. |
119 if (!IsSupported(VFP3) && OS::ArmCpuHasFeature(VFP3)) { | 115 if (!IsSupported(VFP3) && OS::ArmCpuHasFeature(VFP3)) { |
120 // This implementation also sets the VFP flags if runtime | 116 // This implementation also sets the VFP flags if runtime |
121 // detection of VFP returns true. VFPv3 implies ARMv7 and VFP2, see ARM DDI | 117 // detection of VFP returns true. VFPv3 implies ARMv7 and VFP2, see ARM DDI |
122 // 0406B, page A1-6. | 118 // 0406B, page A1-6. |
123 found_by_runtime_probing_ |= 1u << VFP3 | 1u << ARMv7 | 1u << VFP2; | 119 found_by_runtime_probing_ |= 1u << VFP3 | 1u << ARMv7 | 1u << VFP2; |
124 } else if (!IsSupported(VFP2) && OS::ArmCpuHasFeature(VFP2)) { | 120 } else if (!IsSupported(VFP2) && OS::ArmCpuHasFeature(VFP2)) { |
125 found_by_runtime_probing_ |= 1u << VFP2; | 121 found_by_runtime_probing_ |= 1u << VFP2; |
126 } | 122 } |
127 | 123 |
128 if (!IsSupported(ARMv7) && OS::ArmCpuHasFeature(ARMv7)) { | 124 if (!IsSupported(ARMv7) && OS::ArmCpuHasFeature(ARMv7)) { |
129 found_by_runtime_probing_ |= 1u << ARMv7; | 125 found_by_runtime_probing_ |= 1u << ARMv7; |
130 } | 126 } |
131 | 127 |
132 if (!IsSupported(SUDIV) && OS::ArmCpuHasFeature(SUDIV)) { | |
133 found_by_runtime_probing_ |= 1u << SUDIV; | |
134 } | |
135 | |
136 supported_ |= found_by_runtime_probing_; | 128 supported_ |= found_by_runtime_probing_; |
137 #endif | 129 #endif |
138 | 130 |
139 // Assert that VFP3 implies VFP2 and ARMv7. | 131 // Assert that VFP3 implies VFP2 and ARMv7. |
140 ASSERT(!IsSupported(VFP3) || (IsSupported(VFP2) && IsSupported(ARMv7))); | 132 ASSERT(!IsSupported(VFP3) || (IsSupported(VFP2) && IsSupported(ARMv7))); |
141 } | 133 } |
142 | 134 |
143 | 135 |
144 // ----------------------------------------------------------------------------- | 136 // ----------------------------------------------------------------------------- |
145 // Implementation of RelocInfo | 137 // Implementation of RelocInfo |
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1208 | 1200 |
1209 // Multiply instructions. | 1201 // Multiply instructions. |
1210 void Assembler::mla(Register dst, Register src1, Register src2, Register srcA, | 1202 void Assembler::mla(Register dst, Register src1, Register src2, Register srcA, |
1211 SBit s, Condition cond) { | 1203 SBit s, Condition cond) { |
1212 ASSERT(!dst.is(pc) && !src1.is(pc) && !src2.is(pc) && !srcA.is(pc)); | 1204 ASSERT(!dst.is(pc) && !src1.is(pc) && !src2.is(pc) && !srcA.is(pc)); |
1213 emit(cond | A | s | dst.code()*B16 | srcA.code()*B12 | | 1205 emit(cond | A | s | dst.code()*B16 | srcA.code()*B12 | |
1214 src2.code()*B8 | B7 | B4 | src1.code()); | 1206 src2.code()*B8 | B7 | B4 | src1.code()); |
1215 } | 1207 } |
1216 | 1208 |
1217 | 1209 |
1218 void Assembler::mls(Register dst, Register src1, Register src2, Register srcA, | |
1219 Condition cond) { | |
1220 ASSERT(!dst.is(pc) && !src1.is(pc) && !src2.is(pc) && !srcA.is(pc)); | |
1221 emit(cond | B22 | B21 | dst.code()*B16 | srcA.code()*B12 | | |
1222 src2.code()*B8 | B7 | B4 | src1.code()); | |
1223 } | |
1224 | |
1225 | |
1226 void Assembler::sdiv(Register dst, Register src1, Register src2, | |
1227 Condition cond) { | |
1228 ASSERT(!dst.is(pc) && !src1.is(pc) && !src2.is(pc)); | |
1229 emit(cond | B26 | B25| B24 | B20 | dst.code()*B16 | 0xf * B12 | | |
1230 src2.code()*B8 | B4 | src1.code()); | |
1231 } | |
1232 | |
1233 | |
1234 void Assembler::mul(Register dst, Register src1, Register src2, | 1210 void Assembler::mul(Register dst, Register src1, Register src2, |
1235 SBit s, Condition cond) { | 1211 SBit s, Condition cond) { |
1236 ASSERT(!dst.is(pc) && !src1.is(pc) && !src2.is(pc)); | 1212 ASSERT(!dst.is(pc) && !src1.is(pc) && !src2.is(pc)); |
1237 // dst goes in bits 16-19 for this instruction! | 1213 // dst goes in bits 16-19 for this instruction! |
1238 emit(cond | s | dst.code()*B16 | src2.code()*B8 | B7 | B4 | src1.code()); | 1214 emit(cond | s | dst.code()*B16 | src2.code()*B8 | B7 | B4 | src1.code()); |
1239 } | 1215 } |
1240 | 1216 |
1241 | 1217 |
1242 void Assembler::smlal(Register dstL, | 1218 void Assembler::smlal(Register dstL, |
1243 Register dstH, | 1219 Register dstH, |
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2713 | 2689 |
2714 // Since a constant pool was just emitted, move the check offset forward by | 2690 // Since a constant pool was just emitted, move the check offset forward by |
2715 // the standard interval. | 2691 // the standard interval. |
2716 next_buffer_check_ = pc_offset() + kCheckPoolInterval; | 2692 next_buffer_check_ = pc_offset() + kCheckPoolInterval; |
2717 } | 2693 } |
2718 | 2694 |
2719 | 2695 |
2720 } } // namespace v8::internal | 2696 } } // namespace v8::internal |
2721 | 2697 |
2722 #endif // V8_TARGET_ARCH_ARM | 2698 #endif // V8_TARGET_ARCH_ARM |
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