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| 1 // Copyright 2012 the V8 project authors. All rights reserved. | 1 // Copyright 2012 the V8 project authors. All rights reserved. |
| 2 // Redistribution and use in source and binary forms, with or without | 2 // Redistribution and use in source and binary forms, with or without |
| 3 // modification, are permitted provided that the following conditions are | 3 // modification, are permitted provided that the following conditions are |
| 4 // met: | 4 // met: |
| 5 // | 5 // |
| 6 // * Redistributions of source code must retain the above copyright | 6 // * Redistributions of source code must retain the above copyright |
| 7 // notice, this list of conditions and the following disclaimer. | 7 // notice, this list of conditions and the following disclaimer. |
| 8 // * Redistributions in binary form must reproduce the above | 8 // * Redistributions in binary form must reproduce the above |
| 9 // copyright notice, this list of conditions and the following | 9 // copyright notice, this list of conditions and the following |
| 10 // disclaimer in the documentation and/or other materials provided | 10 // disclaimer in the documentation and/or other materials provided |
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| 431 // On X86/X64, values below 32 are bits in EDX, values above 32 are bits in ECX. | 431 // On X86/X64, values below 32 are bits in EDX, values above 32 are bits in ECX. |
| 432 enum CpuFeature { SSE4_1 = 32 + 19, // x86 | 432 enum CpuFeature { SSE4_1 = 32 + 19, // x86 |
| 433 SSE3 = 32 + 0, // x86 | 433 SSE3 = 32 + 0, // x86 |
| 434 SSE2 = 26, // x86 | 434 SSE2 = 26, // x86 |
| 435 CMOV = 15, // x86 | 435 CMOV = 15, // x86 |
| 436 RDTSC = 4, // x86 | 436 RDTSC = 4, // x86 |
| 437 CPUID = 10, // x86 | 437 CPUID = 10, // x86 |
| 438 VFP3 = 1, // ARM | 438 VFP3 = 1, // ARM |
| 439 ARMv7 = 2, // ARM | 439 ARMv7 = 2, // ARM |
| 440 VFP2 = 3, // ARM | 440 VFP2 = 3, // ARM |
| 441 SUDIV = 5, // ARM | |
|
danno
2012/10/01 21:16:17
I changed this to 4 for the commit, I think keepin
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| 441 SAHF = 0, // x86 | 442 SAHF = 0, // x86 |
| 442 FPU = 1}; // MIPS | 443 FPU = 1}; // MIPS |
| 443 | 444 |
| 444 | 445 |
| 445 // Used to specify if a macro instruction must perform a smi check on tagged | 446 // Used to specify if a macro instruction must perform a smi check on tagged |
| 446 // values. | 447 // values. |
| 447 enum SmiCheckType { | 448 enum SmiCheckType { |
| 448 DONT_DO_SMI_CHECK, | 449 DONT_DO_SMI_CHECK, |
| 449 DO_SMI_CHECK | 450 DO_SMI_CHECK |
| 450 }; | 451 }; |
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| 570 | 571 |
| 571 enum ClearExceptionFlag { | 572 enum ClearExceptionFlag { |
| 572 KEEP_EXCEPTION, | 573 KEEP_EXCEPTION, |
| 573 CLEAR_EXCEPTION | 574 CLEAR_EXCEPTION |
| 574 }; | 575 }; |
| 575 | 576 |
| 576 | 577 |
| 577 } } // namespace v8::internal | 578 } } // namespace v8::internal |
| 578 | 579 |
| 579 #endif // V8_V8GLOBALS_H_ | 580 #endif // V8_V8GLOBALS_H_ |
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