ARM validator: continue with extra_load_store_instructions.

src/trusted/validator_arm/armv7.table

Index: src/trusted/validator_arm/armv7.table
diff --git a/src/trusted/validator_arm/armv7.table b/src/trusted/validator_arm/armv7.table
index 8cb2447f3fbdf4b18902e20b0a159029874f473b..d5a620eef5157d09eeda4f4016c310a509507893 100644
--- a/src/trusted/validator_arm/armv7.table
+++ b/src/trusted/validator_arm/armv7.table
@@ -114,7 +114,7 @@ class BreakPointAndConstantPoolHead : Immediate16Use
 class Binary3RegisterImmedShiftedOpRegsNotPc : Binary3RegisterImmedShiftedOp
 class ForbiddenCondNop : UnsafeCondNop
 class ForbiddenUncondNop : UnsafeUncondNop
-class LoadRegisterList : LoadStoreRegisterList      
+class LoadRegisterList : LoadStoreRegisterList
 class LoadStoreVectorRegister : LoadStoreVectorOp
 class LoadVectorRegister : LoadStoreVectorRegister
 class LoadVectorRegisterList : LoadStoreVectorRegisterList
@@ -229,7 +229,7 @@ class Unary2RegisterOpNotRmIsPcNoCondUpdates : Unary2RegisterOpNotRmIsPc
 | 10001      -         -        = Binary2RegisterImmedShiftedTest
                                      => DontCareInst
                                      Tst_Rule_231_A1_P456
-                                     cccc00010001nnnn0000iiiiitt0mmmm 
+                                     cccc00010001nnnn0000iiiiitt0mmmm
 | 10011      -         -        = Binary2RegisterImmedShiftedTest
                                      => DontCareInst
                                      Teq_Rule_228_A1_P450
@@ -311,12 +311,12 @@ class Unary2RegisterOpNotRmIsPcNoCondUpdates : Unary2RegisterOpNotRmIsPc
                            cccc0000011snnnnddddssss0tt1mmmm RegsNotPc
 | 0100x      -        = Binary4RegisterShiftedOp
                            => Defs12To15RdRnRsRmNotPc
-                           Add_Rule_7_A1_P26 
+                           Add_Rule_7_A1_P26
                            cccc0000100snnnnddddssss0tt1mmmm RegsNotPc
 | 0101x      -        = Binary4RegisterShiftedOp
                            => Defs12To15RdRnRsRmNotPc
                            Adc_Rule_3_A1_P18
-                           cccc0000101snnnnddddssss0tt1mmmm RegsNotPc      
+                           cccc0000101snnnnddddssss0tt1mmmm RegsNotPc
 | 0110x      -        = Binary4RegisterShiftedOp
                            => Defs12To15RdRnRsRmNotPc
                            Sbc_Rule_153_A1_P306
@@ -412,7 +412,7 @@ class Unary2RegisterOpNotRmIsPcNoCondUpdates : Unary2RegisterOpNotRmIsPc
 | 0100x      ~1111    = Binary2RegisterImmediateOp
                            => Defs12To15
                            Add_Rule_5_A1_P22
-                           cccc0010100snnnnddddiiiiiiiiiiii 
+                           cccc0010100snnnnddddiiiiiiiiiiii
                            NeitherRdIsPcAndSNorRnIsPcAndNotS
                         # Note: Table says that op=0100x for ADR, but
                         # patterns for ADR do not match (page A8-32).
@@ -508,7 +508,7 @@ class Unary2RegisterOpNotRmIsPcNoCondUpdates : Unary2RegisterOpNotRmIsPc
 | 100x      = Binary4RegisterDualResult
                  => Defs12To19CondsDontCareRdRmRnNotPc
                  Umull_Rule_246_A1_P486
-                 cccc0000100shhhhllllmmmm1001nnnn RegsNotPc                 
+                 cccc0000100shhhhllllmmmm1001nnnn RegsNotPc
 | 101x      = Binary4RegisterDualResult
                  => Defs12To19CondsDontCareRdRmRnNotPc
                  Umlal_Rule_245_A1_P484
@@ -516,7 +516,7 @@ class Unary2RegisterOpNotRmIsPcNoCondUpdates : Unary2RegisterOpNotRmIsPc
 | 110x      = Binary4RegisterDualResult
                  => Defs12To19CondsDontCareRdRmRnNotPc
                  Smull_Rule_179_A1_P356
-                 cccc0000110shhhhllllmmmm1001nnnn RegsNotPc   
+                 cccc0000110shhhhllllmmmm1001nnnn RegsNotPc
 | 111x      = Binary4RegisterDualResult
                  => Defs12To19CondsDontCareRdRmRnNotPc
                  Smlal_Rule_168_A1_P334
@@ -562,7 +562,7 @@ class Unary2RegisterOpNotRmIsPcNoCondUpdates : Unary2RegisterOpNotRmIsPc
 | 01         1     = Binary3RegisterOpAltA
                         => Defs16To19CondsDontCareRdRmRnNotPc
                         Smulwx_Rule_180_A1_P358
-                        cccc00010010dddd0000mmmm1x10nnnn RegsNotPc (v5TE) 
+                        cccc00010010dddd0000mmmm1x10nnnn RegsNotPc (v5TE)
                      # Implements Smlalbb, Smlalbt, Smlaltb, and Smlaltt
                      # where the t/b bits (xx) are in bits 5:6.
 | 10         -     = Binary4RegisterDualResult
@@ -581,7 +581,7 @@ class Unary2RegisterOpNotRmIsPcNoCondUpdates : Unary2RegisterOpNotRmIsPc
 | op2(6:5) op1(24:20) Rn(19:16)
 # Note the following encodings which lead to a different table and aren't
 # handled in this table.
-# TODO(jfb) Should we make them Forbidden?
+# TODO(jfb) Should we mark them as unreachable?
 # 00       -          -         ->data_processing_and_miscellaneous_instructions
 # -        0xx11      -         "
 # 0x       0xx10      -         "
@@ -596,7 +596,7 @@ class Unary2RegisterOpNotRmIsPcNoCondUpdates : Unary2RegisterOpNotRmIsPc
                                   => StoreBasedImmedMemory
                                   Strh_Rule_207_A1_P410
                                   cccc000pu1w0nnnnttttiiii1011iiii
-| "        xx1x1      ~1111     = Load2RegisterImm8Op 
+| "        xx1x1      ~1111     = Load2RegisterImm8Op
                                   => LoadBasedImmedMemory
                                   Ldrh_Rule_74_A1_P152
                                   cccc000pu1w1nnnnttttiiii1011iiii
@@ -616,7 +616,7 @@ class Unary2RegisterOpNotRmIsPcNoCondUpdates : Unary2RegisterOpNotRmIsPc
                                   Ldrd_Rule_66_A1_P136
                                   cccc000pu1w0nnnnttttiiii1101iiii (v5TE)
 | "        "          1111      = Load2RegisterImm8DoubleOp
-                                  => LoadBasedImmedMemoryDouble 
+                                  => LoadBasedImmedMemoryDouble
                                   Ldrd_Rule_67_A1_P138
                                   cccc0001u1001111ttttiiii1101iiii (v5TE)
 | "        xx1x1      ~1111     = Load2RegisterImm8Op
@@ -654,7 +654,10 @@ class Unary2RegisterOpNotRmIsPcNoCondUpdates : Unary2RegisterOpNotRmIsPc
 
 +-- synchronization_primitives (See Section A5.2.10)
 | op(23:20)
-| 0x00      = Deprecated      # SWP, SWPB  TODO(karl): model these? a8-432
+            # SWP/SWPB are OPTIONAL+deprecated in v7 with the Virtualization
+            # Extension, and OBSOLETE+UNDEFINED in v8 aarch32.
+| 0x00      = Deprecated # SWP/SWPB

[Karl, 2012/08/28 19:32:35]

Note: This probably doesn't parse the way you expect. The current parser does
not recognize a pattern if the rule name is omitted. Use "None" if you aren't
going to specify a rule.

[Please use jfb - chromium.org, 2012/08/28 22:19:21]

Done.

+              cccc00010b00nnnntttt00001001tttt
 | 1000      = StoreExclusive3RegisterOp => StoreBasedMemoryRtBits0To3
               Strex_Rule_202_A1_P400
               cccc00011000nnnndddd11111001tttt (v6)
@@ -673,14 +676,14 @@ class Unary2RegisterOpNotRmIsPcNoCondUpdates : Unary2RegisterOpNotRmIsPc
               cccc00011100nnnndddd11111001tttt (v6K)
 | 1101      = LoadExclusive2RegisterOp => LoadBasedMemory
               Ldrexb_Rule_70_A1_P144
-              cccc00011101nnnndddd111110011111 (v6K)
+              cccc00011101nnnntttt111110011111 (v6K)
 | 1110      = StoreExclusive3RegisterOp  => StoreBasedMemoryRtBits0To3
               Strexh_Rule_205_A1_P406
               cccc00011110nnnndddd11111001tttt (v6K)
 | 1111      = LoadExclusive2RegisterOp => LoadBasedMemory
               Ldrexh_Rule_72_A1_P148
               cccc00011111nnnntttt111110011111 (v6K)
-| else:     = Undefined (v6K)            # Note on page A5-16
+| else:     = Undefined # Note on page A5-16
 +--
 
 +-- msr_immediate_and_hints (See Section A5.2.11)
@@ -715,7 +718,11 @@ class Unary2RegisterOpNotRmIsPcNoCondUpdates : Unary2RegisterOpNotRmIsPc
                                  # conditions flag is always changed, which
                                  # is a safe presumption.
                                  Msr_Rule_103_A1_P208
-| "      1x00       "          "
+                                 cccc0011001001001111iiiiiiiiiiii

[Karl, 2012/08/28 19:32:35]

This action can be repeated with " (on the next line) if you replace the pattern
with cccc00110010mm001111iiiiiiiiiiii. This is now allowable due to the recent
change I added.

I assume the issue you have is with the fact that mask 00 is not allowed. We
should consider this a "safety" issue that applies to both rows, rather than
separate patterns. However, our tables are not there yet to allow (simple)
specification of safety rules. Hence, if you are going to leave the patterns the
way you have specified, add a TODO to explain this.

[Please use jfb - chromium.org, 2012/08/28 22:19:21]

Done (added TODO).

+| "      1x00       "          = MoveImmediate12ToApsr => DontCareInst
+                                 # Same note as above.
+                                 Msr_Rule_103_A1_P208
+                                 cccc001100101x001111iiiiiiiiiiii
 | "      xx01       -          = ForbiddenCondNop => Forbidden
                                  Msr_Rule_B6_1_6_A1_PB6_12
                                  cccc00110010ii011111iiiiiiiiiiii
@@ -732,45 +739,57 @@ class Unary2RegisterOpNotRmIsPcNoCondUpdates : Unary2RegisterOpNotRmIsPc
 +--
 
 +-- miscellaneous_instructions (See Section A5.2.12)
-| op2(6:4) op(22:21) op1(19:16)
-| 000      x0        xxxx       = Unary1RegisterSet
-                                  Mrs_Rule_102_A1_P206_Or_B6_10
-                                  cccc00010r001111dddd000000000000
-| "        01        xx00       = Unary1RegisterUse
-                                  Msr_Rule_104_A1_P210
-                                  cccc00010010mm00111100000000nnnn
-| "        01        xx01       = ForbiddenCondNop => Forbidden
-                                  Msr_Rule_B6_1_7_P14
-                                  cccc00010010mm01111100000000nnnn
-| "        "         xx1x       = ForbiddenCondNop => Forbidden
-                                  Msr_Rule_B6_1_7_P14
-                                  cccc00010010mm1m111100000000nnnn
-| "        11        -          = ForbiddenCondNop => Forbidden
-                                  Msr_Rule_B6_1_7_P14
-                                  cccc00010110mmmm111100000000nnnn
-| 001      01        -          = BranchToRegister => BxBlx
-                                  Bx_Rule_25_A1_P62
-                                  cccc000100101111111111110001mmmm (v4T)
-| "        11        -          = Unary2RegisterOpNotRmIsPc
-                                  => Defs12To15RdRnNotPc
-                                  Clz_Rule_31_A1_P72
-                                  cccc000101101111dddd11110001mmmm (v6)
-| 010      01        -          = ForbiddenCondNop => Forbidden
-                                  Bxj_Rule_26_A1_P64
-                                  cccc000100101111111111110010mmmm
-| 011      01        -          = BranchToRegister => BxBlx
-                                  Blx_Rule_24_A1_P60
-                                  cccc000100101111111111110011mmmm
-                                  RegsNotPc (v5T)
-| 101      -         -          ->saturating_addition_and_subtraction
-| 111      01        -          = BreakPointAndConstantPoolHead
-                                  => Breakpoint
-                                  Bkpt_Rule_22_A1_P56
-                                  cccc00010010iiiiiiiiiiii0111iiii (v5T)
-| 111      11        -          = ForbiddenCondNop => Forbidden
-                                  Smc_Rule_B6_1_9_P18
-                                  cccc000101100000000000000111mmmm
-| else:                         = Undefined     # Note on page A5-18
+| op2(6:4) B(9) op(22:21) op1(19:16)
+| 000      1    x0        xxxx       = ForbiddenCondNop => Forbidden
+                                       # MSR (Banked register)

[Karl, 2012/08/28 19:32:35]

Warning: This isn't probably parsing the way you think. The current parser will
only recognize a pattern if a rule name is specified (or None is used as a
placeholder to communicate that there isn't a rule name).

[Please use jfb - chromium.org, 2012/08/28 22:19:21]

Done.

+                                       cccc00010r00mmmmdddd001m00000000 (v7VE)
+| "        "    x1        "          = ForbiddenCondNop => Forbidden
+                                       # MSR (Banked register)

[Karl, 2012/08/28 19:32:35]

Same here.

[Please use jfb - chromium.org, 2012/08/28 22:19:21]

Done.

+                                       cccc00010r10mmmm1111001m0000nnnn (v7VE)
+| "        0    x0        xxxx       = Unary1RegisterSet
+                                       Mrs_Rule_102_A1_P206_Or_B6_10
+                                       cccc00010r001111dddd000000000000
+| "        "    01        xx00       = Unary1RegisterUse
+                                       Msr_Rule_104_A1_P210
+                                       cccc00010010mm00111100000000nnnn
+| "        "    01        xx01       = ForbiddenCondNop => Forbidden
+                                       Msr_Rule_B6_1_7_P14
+                                       cccc00010010mm01111100000000nnnn
+| "        "    "         xx1x       = ForbiddenCondNop => Forbidden
+                                       Msr_Rule_B6_1_7_P14
+                                       cccc00010010mm1m111100000000nnnn
+| "        "    11        -          = ForbiddenCondNop => Forbidden
+                                       Msr_Rule_B6_1_7_P14
+                                       cccc00010110mmmm111100000000nnnn
+| 001      -    01        -          = BranchToRegister => BxBlx
+                                       Bx_Rule_25_A1_P62
+                                       cccc000100101111111111110001mmmm (v4T)
+| "        -    11        -          = Unary2RegisterOpNotRmIsPc
+                                       => Defs12To15RdRnNotPc
+                                       Clz_Rule_31_A1_P72
+                                       cccc000101101111dddd11110001mmmm (v5T)
+| 010      -    01        -          = ForbiddenCondNop => Forbidden
+                                       Bxj_Rule_26_A1_P64
+                                       cccc000100101111111111110010mmmm (v5TEJ)
+| 011      -    01        -          = BranchToRegister => BxBlx
+                                       Blx_Rule_24_A1_P60
+                                       cccc000100101111111111110011mmmm
+                                       RegsNotPc (v5T)
+| 101      -    -         -          ->saturating_addition_and_subtraction
+| 110      -    11        -          = ForbiddenCondNop => Forbidden
+                                       # ERET
+                                       cccc0001011000000000000001101110 (v7VE)
+| 111      -    01        -          = BreakPointAndConstantPoolHead
+                                       => Breakpoint
+                                       Bkpt_Rule_22_A1_P56
+                                       cccc00010010iiiiiiiiiiii0111iiii (v5T)
+| "        -    10        -          = ForbiddenCondNop => Forbidden
+                                       # HVC
+                                       cccc00010100iiiiiiiiiiii0111iiii (v7VE)
+| "        -    11        -          = ForbiddenCondNop => Forbidden
+                                       Smc_Rule_B6_1_9_P18
+                                       cccc000101100000000000000111iiii (SE)
+| else:                              = Undefined     # Note on page A5-18
 +--
 
 +-- load_store_word_and_unsigned_byte (See Section A5.3)
@@ -779,7 +798,7 @@ class Unary2RegisterOpNotRmIsPcNoCondUpdates : Unary2RegisterOpNotRmIsPc
 | A(25) op1(24:20) B(4) Rn(19:16)  op1_repeated(24:20)
 | 0     xx0x0      -    -          ~0x010 -> load_store_word_and_unsigned_byte_str_or_push
 | 1     xx0x0      0    -          ~0x010
-                                   = Store3RegisterImm5Op 
+                                   = Store3RegisterImm5Op
                                    => StoreBasedOffsetMemory
                                    Str_Rule_195_A1_P386
                                    cccc011pd0w0nnnnttttiiiiitt0mmmm
@@ -792,7 +811,7 @@ class Unary2RegisterOpNotRmIsPcNoCondUpdates : Unary2RegisterOpNotRmIsPc
                                    => LoadBasedImmedMemory
                                    Ldr_Rule_58_A1_P120
                                    cccc010pd0w1nnnnttttiiiiiiiiiiii NotRnIsPc
-| "     xx0x1      "    1111       ~0x011  
+| "     xx0x1      "    1111       ~0x011
                                    = Load2RegisterImm12Op
                                    => LoadBasedImmedMemory
                                    Ldr_Rule_59_A1_P122
@@ -1291,11 +1310,11 @@ class Unary2RegisterOpNotRmIsPcNoCondUpdates : Unary2RegisterOpNotRmIsPc
 +--
 
 +-- coprocessor_instructions_and_supervisor_call (See Section A5.6)
-# Note: We currently only allow floating point (and advanced SIMD) 
+# Note: We currently only allow floating point (and advanced SIMD)
 # coprocessor operations (coproc=101x).
 # Note: Column op1 is repeated so that the first three rows can define
 # (anded) multiple test conditions for this row.
-| op1(25:20) op(4) coproc(11:8) Rn(19:16) op1_repeated(25:20) 
+| op1(25:20) op(4) coproc(11:8) Rn(19:16) op1_repeated(25:20)
 | 0xxxxx     -     101x         -         ~000x0x
                    -> extension_register_load_store_instructions
 | 0xxxx0     -     ~101x           -      ~000x0x
@@ -1363,7 +1382,7 @@ class Unary2RegisterOpNotRmIsPcNoCondUpdates : Unary2RegisterOpNotRmIsPc
 +--
 
 +-- other_floating_point_data_processing_instructions (A7.5 Table A7-17, page 17-25)
-# Other VPD data-processing, CDP instructions for coprocessors 10/11. 
+# Other VPD data-processing, CDP instructions for coprocessors 10/11.
 #
 # Note: Currently, all instructions use class CoprocessorOp
 # to follow what the previous version of the ARM validator did.
@@ -1508,7 +1527,7 @@ class Unary2RegisterOpNotRmIsPcNoCondUpdates : Unary2RegisterOpNotRmIsPc
 +--
 
 +-- unconditional_instructions (See Section A5.7)
-# Note: We currently only allow floating point (and advanced SIMD) 
+# Note: We currently only allow floating point (and advanced SIMD)
 # coprocessor operations (coproc=101x).
 #
 # Note: Most instructions in this table are forbidden because they