ARM validator: continue with extra_load_store_instructions.

src/trusted/validator_arm/armv7.table

 # ARMv7 Instruction Encodings
 #
 # This table is derived from the "ARM Architecture Reference Manual, ARMv7-A
 # and ARMv7-R edition" and is used here with the permission of ARM Limited.
 # Reproduction for purposes other than the development and distribution of
 # Native Client may require the explicit permission of ARM Limited.
 
 # This file defines the Native Client "instruction classes" assigned to every
 # possible ARMv7 instruction encoding.  It is organized into a series of tables,
 # and directly parallels the ARM Architecture Reference Manual cited above.
@@ skipping 96 matching lines @@
 # By providing this information, the generator can pick out
 # the corresponding baseline class tester to use, and does
 # not need to define separate testers for derived classes of
 # the baseline class tester.
 # #############################################################
 
 class BreakPointAndConstantPoolHead : Immediate16Use
 class Binary3RegisterImmedShiftedOpRegsNotPc : Binary3RegisterImmedShiftedOp
 class ForbiddenCondNop : UnsafeCondNop
 class ForbiddenUncondNop : UnsafeUncondNop
-class LoadRegisterList : LoadStoreRegisterList      
+class LoadRegisterList : LoadStoreRegisterList
 class LoadStoreVectorRegister : LoadStoreVectorOp
 class LoadVectorRegister : LoadStoreVectorRegister
 class LoadVectorRegisterList : LoadStoreVectorRegisterList
 class Load3RegisterDoubleOp : LoadStore3RegisterDoubleOp
 class Load2RegisterImm8DoubleOp : LoadStore2RegisterImm8DoubleOp
 class Load2RegisterImm8Op : LoadStore2RegisterImm8Op
 class Load2RegisterImm12Op : LoadStore2RegisterImm12Op
 class Load3RegisterImm5Op : LoadStore3RegisterImm5Op
 class Load3RegisterOp : LoadStore3RegisterOp
 class MaskedBinary2RegisterImmediateOp : Binary2RegisterImmediateOp
@@ skipping 94 matching lines @@
                                      cccc0000110unnnnddddiiiiitt0mmmm
                                      NotRdIsPcAndS
 | 0111x      -         -        = Binary3RegisterImmedShiftedOp
                                      => Defs12To15
                                      Rsc_Rule_146_A1_P292
                                      cccc0000111unnnnddddiiiiitt0mmmm
                                      NotRdIsPcAndS
 | 10001      -         -        = Binary2RegisterImmedShiftedTest
                                      => DontCareInst
                                      Tst_Rule_231_A1_P456
-                                     cccc00010001nnnn0000iiiiitt0mmmm 
+                                     cccc00010001nnnn0000iiiiitt0mmmm
 | 10011      -         -        = Binary2RegisterImmedShiftedTest
                                      => DontCareInst
                                      Teq_Rule_228_A1_P450
                                      cccc00010011nnnn0000iiiiitt0mmmm
 | 10101      -         -        = Binary2RegisterImmedShiftedTest
                                      => DontCareInst
                                      Cmp_Rule_36_A1_P82
                                      cccc00010101nnnn0000iiiiitt0mmmm
 | 10111      -         -        = Binary2RegisterImmedShiftedTest
                                      => DontCareInst
@@ skipping 61 matching lines @@
 | 0010x      -        = Binary4RegisterShiftedOp
                            => Defs12To15RdRnRsRmNotPc
                            Sub_Rule_214_A1_P424
                            cccc0000010snnnnddddssss0tt1mmmm RegsNotPc
 | 0011x      -        = Binary4RegisterShiftedOp
                             => Defs12To15RdRnRsRmNotPc
                            Rsb_Rule_144_A1_P288
                            cccc0000011snnnnddddssss0tt1mmmm RegsNotPc
 | 0100x      -        = Binary4RegisterShiftedOp
                            => Defs12To15RdRnRsRmNotPc
-                           Add_Rule_7_A1_P26 
+                           Add_Rule_7_A1_P26
                            cccc0000100snnnnddddssss0tt1mmmm RegsNotPc
 | 0101x      -        = Binary4RegisterShiftedOp
                            => Defs12To15RdRnRsRmNotPc
                            Adc_Rule_3_A1_P18
-                           cccc0000101snnnnddddssss0tt1mmmm RegsNotPc      
+                           cccc0000101snnnnddddssss0tt1mmmm RegsNotPc
 | 0110x      -        = Binary4RegisterShiftedOp
                            => Defs12To15RdRnRsRmNotPc
                            Sbc_Rule_153_A1_P306
                            cccc0000110snnnnddddssss0tt1mmmm RegsNotPc
 | 0111x      -        = Binary4RegisterShiftedOp
                            => Defs12To15RdRnRsRmNotPc
                            Rsc_Rule_147_A1_P294
                            cccc0000111snnnnddddssss0tt1mmmm RegsNotPc
 # TODO(jfb) op==10xx0 should be unreachable from here:
 #           the previous table should handle it.
@@ skipping 75 matching lines @@
                            Adr_Rule_10_A2_P32
                            cccc001001001111ddddiiiiiiiiiiii
 | 00101      1111     = Forbidden # SUBS PC, LR and related instructions
 | 0011x      -        = Binary2RegisterImmediateOp
                            => Defs12To15
                            Rsb_Rule_142_A1_P284
                            cccc0010011snnnnddddiiiiiiiiiiii NotRdIsPcAndS
 | 0100x      ~1111    = Binary2RegisterImmediateOp
                            => Defs12To15
                            Add_Rule_5_A1_P22
-                           cccc0010100snnnnddddiiiiiiiiiiii 
+                           cccc0010100snnnnddddiiiiiiiiiiii
                            NeitherRdIsPcAndSNorRnIsPcAndNotS
                         # Note: Table says that op=0100x for ADR, but
                         # patterns for ADR do not match (page A8-32).
                         # Causes parsing conflicts with ADD (previous
                         # row). Added restriction to ADR that bit 20
                         # (updates flags register) must be 0 (rather than
                         # x), to match what is on A8.6.10 (page A8-32).
                         # Note that this also matches restrictions of
                         # A8.6.5 (page A8-22).
 | 01000      1111     = Unary1RegisterImmediateOp
@@ skipping 75 matching lines @@
                  cccc00000100hhhhllllmmmm1001nnnn RegsNotPc (v6)
 | 0101      = Undefined
 | 0110      = Binary4RegisterDualOp
                  => Defs16To19CondsDontCareRdRaRmRnNotPc
                  Mls_Rule_95_A1_P192
                  cccc00000110ddddaaaammmm1001nnnn RegsNotPc (v6T2)
 | 0111      = Undefined
 | 100x      = Binary4RegisterDualResult
                  => Defs12To19CondsDontCareRdRmRnNotPc
                  Umull_Rule_246_A1_P486
-                 cccc0000100shhhhllllmmmm1001nnnn RegsNotPc                 
+                 cccc0000100shhhhllllmmmm1001nnnn RegsNotPc
 | 101x      = Binary4RegisterDualResult
                  => Defs12To19CondsDontCareRdRmRnNotPc
                  Umlal_Rule_245_A1_P484
                  cccc0000101shhhhllllmmmm1001nnnn RegsNotPc
 | 110x      = Binary4RegisterDualResult
                  => Defs12To19CondsDontCareRdRmRnNotPc
                  Smull_Rule_179_A1_P356
-                 cccc0000110shhhhllllmmmm1001nnnn RegsNotPc   
+                 cccc0000110shhhhllllmmmm1001nnnn RegsNotPc
 | 111x      = Binary4RegisterDualResult
                  => Defs12To19CondsDontCareRdRmRnNotPc
                  Smlal_Rule_168_A1_P334
                  cccc0000111shhhhllllmmmm1001nnnn RegsNotPc
 +--
 
 +-- saturating_addition_and_subtraction (See Section A5.2.6)
 | op(22:21)
 | 00        = Binary3RegisterOpAltB
               => Defs12To15CondsDontCareRnRdRmNotPc
@@ skipping 25 matching lines @@
                      # bit is in bit 6.
 | 01         0     = Binary4RegisterDualOp
                         => Defs16To19CondsDontCareRdRaRmRnNotPc
                         Smlawx_Rule_171_A1_340
                         cccc00010010ddddaaaammmm1x00nnnn RegsNotPc (v5TE)
                      # Implements Smulwb and Smulwt where the t/b (x)
                      # bit is in bit 6.
 | 01         1     = Binary3RegisterOpAltA
                         => Defs16To19CondsDontCareRdRmRnNotPc
                         Smulwx_Rule_180_A1_P358
-                        cccc00010010dddd0000mmmm1x10nnnn RegsNotPc (v5TE) 
+                        cccc00010010dddd0000mmmm1x10nnnn RegsNotPc (v5TE)
                      # Implements Smlalbb, Smlalbt, Smlaltb, and Smlaltt
                      # where the t/b bits (xx) are in bits 5:6.
 | 10         -     = Binary4RegisterDualResult
                         => Defs12To19CondsDontCareRdRmRnNotPc
                         Smlalxx_Rule_169_A1_P336
                         cccc00010100hhhhllllmmmm1xx0nnnn RegsNotPc (v5TE)
                      # Implements Smulbb, Smulbt, Smultb, and Smultt
                      # where the t/b bits (xx) are in bits 5:6.
 | 11         -     = Binary3RegisterOpAltA
                         => Defs16To19CondsDontCareRdRmRnNotPc
                         Smulxx_Rule_178_P354
                         cccc00010110dddd0000mmmm1xx0nnnn RegsNotPc (v5TE)
 +--
 
 +-- extra_load_store_instructions (See Section A5.2.8)
 | op2(6:5) op1(24:20) Rn(19:16)
 # Note the following encodings which lead to a different table and aren't
 # handled in this table.
-# TODO(jfb) Should we make them Forbidden?
+# TODO(jfb) Should we mark them as unreachable?
 # 00       -          -         ->data_processing_and_miscellaneous_instructions
 # -        0xx11      -         "
 # 0x       0xx10      -         "
 #
 | 01       xx0x0      -         = Store3RegisterOp => StoreBasedOffsetMemory
                                   Strh_Rule_208_A1_P412
                                   cccc000pu0w0nnnntttt00001011mmmm
 | "        xx0x1      -         = Load3RegisterOp => LoadBasedOffsetMemory
                                   Ldrh_Rule_76_A1_P156
                                   cccc000pu0w1nnnntttt00001011mmmm
 | "        xx1x0      -         = Store2RegisterImm8Op
                                   => StoreBasedImmedMemory
                                   Strh_Rule_207_A1_P410
                                   cccc000pu1w0nnnnttttiiii1011iiii
-| "        xx1x1      ~1111     = Load2RegisterImm8Op 
+| "        xx1x1      ~1111     = Load2RegisterImm8Op
                                   => LoadBasedImmedMemory
                                   Ldrh_Rule_74_A1_P152
                                   cccc000pu1w1nnnnttttiiii1011iiii
 | "        "          1111      = Load2RegisterImm8Op
                                   => LoadBasedImmedMemory
                                   Ldrh_Rule_75_A1_P154
                                   cccc0001u1011111ttttiiii1011iiii
 | 10       xx0x0      -         = Load3RegisterDoubleOp
                                   => LoadBasedOffsetMemoryDouble
                                   Ldrd_Rule_68_A1_P140
                                   cccc000pu0w0nnnntttt00001101mmmm (v5TE)
 | "        xx0x1      -         = Load3RegisterOp => LoadBasedOffsetMemory
                                   Ldrsb_Rule_80_A1_P164
                                   cccc000pu0w1nnnntttt00001101mmmm
 | "        xx1x0      ~1111     = Load2RegisterImm8DoubleOp
                                   => LoadBasedImmedMemoryDouble
                                   Ldrd_Rule_66_A1_P136
                                   cccc000pu1w0nnnnttttiiii1101iiii (v5TE)
 | "        "          1111      = Load2RegisterImm8DoubleOp
-                                  => LoadBasedImmedMemoryDouble 
+                                  => LoadBasedImmedMemoryDouble
                                   Ldrd_Rule_67_A1_P138
                                   cccc0001u1001111ttttiiii1101iiii (v5TE)
 | "        xx1x1      ~1111     = Load2RegisterImm8Op
                                   => LoadBasedImmedMemory
                                   Ldrsb_Rule_78_A1_P160
                                   cccc000pu1w1nnnnttttiiii1101iiii
 | "        "          1111      = Load2RegisterImm8Op
                                   => LoadBasedImmedMemory
                                   ldrsb_Rule_79_A1_162
                                   cccc0001u1011111ttttiiii1101iiii
@@ skipping 17 matching lines @@
                                   Ldrsh_Rule_83_A1_P170
                                   cccc0001u1011111ttttiiii1111iiii
 +--
 
 # extra_load_store_instructions_unpriviledged (See section A5.2.9)
 # Table omitted: modeled as Forbidden.
 # They are not expected in user code.
 
 +-- synchronization_primitives (See Section A5.2.10)
 | op(23:20)
-| 0x00      = Deprecated      # SWP, SWPB  TODO(karl): model these? a8-432
+            # SWP/SWPB are OPTIONAL+deprecated in v7 with the Virtualization
+            # Extension, and OBSOLETE+UNDEFINED in v8 aarch32.
+| 0x00      = Deprecated # SWP/SWPB

[Karl, 2012/08/28 19:32:35]

Note: This probably doesn't parse the way you expect. The current parser does
not recognize a pattern if the rule name is omitted. Use "None" if you aren't
going to specify a rule.

[Please use jfb - chromium.org, 2012/08/28 22:19:21]

Done.

+              cccc00010b00nnnntttt00001001tttt
 | 1000      = StoreExclusive3RegisterOp => StoreBasedMemoryRtBits0To3
               Strex_Rule_202_A1_P400
               cccc00011000nnnndddd11111001tttt (v6)
 | 1001      = LoadExclusive2RegisterOp => LoadBasedMemory
               Ldrex_Rule_69_A1_P142
               cccc00011001nnnntttt111110011111 (v6)
 | 1010      = StoreExclusive3RegisterDoubleOp
               => StoreBasedMemoryDoubleRtBits0To3
               Strexd_Rule_204_A1_P404
               cccc00011010nnnndddd11111001tttt (v6K)
 | 1011      = LoadExclusive2RegisterDoubleOp => LoadBasedMemoryDouble
               Ldrexd_Rule_71_A1_P146
               cccc00011011nnnntttt111110011111 (v6K)
 | 1100      = StoreExclusive3RegisterOp => StoreBasedMemoryRtBits0To3
               Strexb_Rule_203_A1_P402
               cccc00011100nnnndddd11111001tttt (v6K)
 | 1101      = LoadExclusive2RegisterOp => LoadBasedMemory
               Ldrexb_Rule_70_A1_P144
-              cccc00011101nnnndddd111110011111 (v6K)
+              cccc00011101nnnntttt111110011111 (v6K)
 | 1110      = StoreExclusive3RegisterOp  => StoreBasedMemoryRtBits0To3
               Strexh_Rule_205_A1_P406
               cccc00011110nnnndddd11111001tttt (v6K)
 | 1111      = LoadExclusive2RegisterOp => LoadBasedMemory
               Ldrexh_Rule_72_A1_P148
               cccc00011111nnnntttt111110011111 (v6K)
-| else:     = Undefined (v6K)            # Note on page A5-16
+| else:     = Undefined # Note on page A5-16
 +--
 
 +-- msr_immediate_and_hints (See Section A5.2.11)
 | op(22) op1(19:16) op2(7:0)
 | 0      0000       0000_0000  = CondNop => DontCareInst
                                  Nop_Rule_110_A1_P222
                                  cccc0011001000001111000000000000 (v6K,v6T2)
 | "      "          0000_0001  = CondNop => DontCareInst
                                  Yield_Rule_413_A1_P812
                                  cccc0011001000001111000000000001 (v6K)
@@ skipping 14 matching lines @@
                                  Sev_Rule_158_A1_P316
                                  cccc0011001000001111000000000100 (v6K)
 | "      "          1111_xxxx  = CondNop => DontCareInst
                                  Dbg_Rule_40_A1_P88
                                  cccc001100100000111100001111iiii (v7)
 | "      0100       -          = MoveImmediate12ToApsr => DontCareInst
                                  # Note: DontCareInst will act like the
                                  # conditions flag is always changed, which
                                  # is a safe presumption.
                                  Msr_Rule_103_A1_P208
-| "      1x00       "          "
+                                 cccc0011001001001111iiiiiiiiiiii

[Karl, 2012/08/28 19:32:35]

This action can be repeated with " (on the next line) if you replace the pattern
with cccc00110010mm001111iiiiiiiiiiii. This is now allowable due to the recent
change I added.

I assume the issue you have is with the fact that mask 00 is not allowed. We
should consider this a "safety" issue that applies to both rows, rather than
separate patterns. However, our tables are not there yet to allow (simple)
specification of safety rules. Hence, if you are going to leave the patterns the
way you have specified, add a TODO to explain this.

[Please use jfb - chromium.org, 2012/08/28 22:19:21]

Done (added TODO).

+| "      1x00       "          = MoveImmediate12ToApsr => DontCareInst
+                                 # Same note as above.
+                                 Msr_Rule_103_A1_P208
+                                 cccc001100101x001111iiiiiiiiiiii
 | "      xx01       -          = ForbiddenCondNop => Forbidden
                                  Msr_Rule_B6_1_6_A1_PB6_12
                                  cccc00110010ii011111iiiiiiiiiiii
                                  # MSR(immediate), ring0 version
 | "      xx1x       -          = ForbiddenCondNop => Forbidden
                                  Msr_Rule_B6_1_6_A1_PB6_12
                                  cccc00110010ii1i1111iiiiiiiiiiii
                                  # MSR(immediate), ring0 version
 | 1      -          -          = ForbiddenCondNop => Forbidden
                                  Msr_Rule_B6_1_6_A1_PB6_12
                                  cccc00110110iiii1111iiiiiiiiiiii
                                  # MSR(immediate), ring0 version
 | else:                        = Forbidden  # Unallocated hints, page A5-17
 +--
 
 +-- miscellaneous_instructions (See Section A5.2.12)
-| op2(6:4) op(22:21) op1(19:16)
-| 000      x0        xxxx       = Unary1RegisterSet
-                                  Mrs_Rule_102_A1_P206_Or_B6_10
-                                  cccc00010r001111dddd000000000000
-| "        01        xx00       = Unary1RegisterUse
-                                  Msr_Rule_104_A1_P210
-                                  cccc00010010mm00111100000000nnnn
-| "        01        xx01       = ForbiddenCondNop => Forbidden
-                                  Msr_Rule_B6_1_7_P14
-                                  cccc00010010mm01111100000000nnnn
-| "        "         xx1x       = ForbiddenCondNop => Forbidden
-                                  Msr_Rule_B6_1_7_P14
-                                  cccc00010010mm1m111100000000nnnn
-| "        11        -          = ForbiddenCondNop => Forbidden
-                                  Msr_Rule_B6_1_7_P14
-                                  cccc00010110mmmm111100000000nnnn
-| 001      01        -          = BranchToRegister => BxBlx
-                                  Bx_Rule_25_A1_P62
-                                  cccc000100101111111111110001mmmm (v4T)
-| "        11        -          = Unary2RegisterOpNotRmIsPc
-                                  => Defs12To15RdRnNotPc
-                                  Clz_Rule_31_A1_P72
-                                  cccc000101101111dddd11110001mmmm (v6)
-| 010      01        -          = ForbiddenCondNop => Forbidden
-                                  Bxj_Rule_26_A1_P64
-                                  cccc000100101111111111110010mmmm
-| 011      01        -          = BranchToRegister => BxBlx
-                                  Blx_Rule_24_A1_P60
-                                  cccc000100101111111111110011mmmm
-                                  RegsNotPc (v5T)
-| 101      -         -          ->saturating_addition_and_subtraction
-| 111      01        -          = BreakPointAndConstantPoolHead
-                                  => Breakpoint
-                                  Bkpt_Rule_22_A1_P56
-                                  cccc00010010iiiiiiiiiiii0111iiii (v5T)
-| 111      11        -          = ForbiddenCondNop => Forbidden
-                                  Smc_Rule_B6_1_9_P18
-                                  cccc000101100000000000000111mmmm
-| else:                         = Undefined     # Note on page A5-18
+| op2(6:4) B(9) op(22:21) op1(19:16)
+| 000      1    x0        xxxx       = ForbiddenCondNop => Forbidden
+                                       # MSR (Banked register)

[Karl, 2012/08/28 19:32:35]

Warning: This isn't probably parsing the way you think. The current parser will
only recognize a pattern if a rule name is specified (or None is used as a
placeholder to communicate that there isn't a rule name).

[Please use jfb - chromium.org, 2012/08/28 22:19:21]

Done.

+                                       cccc00010r00mmmmdddd001m00000000 (v7VE)
+| "        "    x1        "          = ForbiddenCondNop => Forbidden
+                                       # MSR (Banked register)

[Karl, 2012/08/28 19:32:35]

Same here.

[Please use jfb - chromium.org, 2012/08/28 22:19:21]

Done.

+                                       cccc00010r10mmmm1111001m0000nnnn (v7VE)
+| "        0    x0        xxxx       = Unary1RegisterSet
+                                       Mrs_Rule_102_A1_P206_Or_B6_10
+                                       cccc00010r001111dddd000000000000
+| "        "    01        xx00       = Unary1RegisterUse
+                                       Msr_Rule_104_A1_P210
+                                       cccc00010010mm00111100000000nnnn
+| "        "    01        xx01       = ForbiddenCondNop => Forbidden
+                                       Msr_Rule_B6_1_7_P14
+                                       cccc00010010mm01111100000000nnnn
+| "        "    "         xx1x       = ForbiddenCondNop => Forbidden
+                                       Msr_Rule_B6_1_7_P14
+                                       cccc00010010mm1m111100000000nnnn
+| "        "    11        -          = ForbiddenCondNop => Forbidden
+                                       Msr_Rule_B6_1_7_P14
+                                       cccc00010110mmmm111100000000nnnn
+| 001      -    01        -          = BranchToRegister => BxBlx
+                                       Bx_Rule_25_A1_P62
+                                       cccc000100101111111111110001mmmm (v4T)
+| "        -    11        -          = Unary2RegisterOpNotRmIsPc
+                                       => Defs12To15RdRnNotPc
+                                       Clz_Rule_31_A1_P72
+                                       cccc000101101111dddd11110001mmmm (v5T)
+| 010      -    01        -          = ForbiddenCondNop => Forbidden
+                                       Bxj_Rule_26_A1_P64
+                                       cccc000100101111111111110010mmmm (v5TEJ)
+| 011      -    01        -          = BranchToRegister => BxBlx
+                                       Blx_Rule_24_A1_P60
+                                       cccc000100101111111111110011mmmm
+                                       RegsNotPc (v5T)
+| 101      -    -         -          ->saturating_addition_and_subtraction
+| 110      -    11        -          = ForbiddenCondNop => Forbidden
+                                       # ERET
+                                       cccc0001011000000000000001101110 (v7VE)
+| 111      -    01        -          = BreakPointAndConstantPoolHead
+                                       => Breakpoint
+                                       Bkpt_Rule_22_A1_P56
+                                       cccc00010010iiiiiiiiiiii0111iiii (v5T)
+| "        -    10        -          = ForbiddenCondNop => Forbidden
+                                       # HVC
+                                       cccc00010100iiiiiiiiiiii0111iiii (v7VE)
+| "        -    11        -          = ForbiddenCondNop => Forbidden
+                                       Smc_Rule_B6_1_9_P18
+                                       cccc000101100000000000000111iiii (SE)
+| else:                              = Undefined     # Note on page A5-18
 +--
 
 +-- load_store_word_and_unsigned_byte (See Section A5.3)
 # Note: Column op1 is repeated so that several rows can define
 # (anded) multiple test conditions for this row.
 | A(25) op1(24:20) B(4) Rn(19:16)  op1_repeated(24:20)
 | 0     xx0x0      -    -          ~0x010 -> load_store_word_and_unsigned_byte_str_or_push
 | 1     xx0x0      0    -          ~0x010
-                                   = Store3RegisterImm5Op 
+                                   = Store3RegisterImm5Op
                                    => StoreBasedOffsetMemory
                                    Str_Rule_195_A1_P386
                                    cccc011pd0w0nnnnttttiiiiitt0mmmm
 # STRT (rule 210, A1 and A2, page 416) define unprivledge stores, which
 # NaCl doesn't allow.
 | 0     0x010      -    -          - = Forbidden
 | 1     0x010      0    -          - = Forbidden
 | 0     xx0x1      -    ~1111      ~0x011
                                    = Load2RegisterImm12Op
                                    => LoadBasedImmedMemory
                                    Ldr_Rule_58_A1_P120
                                    cccc010pd0w1nnnnttttiiiiiiiiiiii NotRnIsPc
-| "     xx0x1      "    1111       ~0x011  
+| "     xx0x1      "    1111       ~0x011
                                    = Load2RegisterImm12Op
                                    => LoadBasedImmedMemory
                                    Ldr_Rule_59_A1_P122
                                    cccc0101d0011111ttttiiiiiiiiiiii
 | 1     xx0x1      0    -          ~0x011
                                    = Load3RegisterImm5Op => LoadBasedOffsetMemory
                                    Ldr_Rule_60_A1_P124
                                    cccc011pd0w1nnnnttttiiiiitt0mmmm
 # LDRT (rule 86, A1 and A2, page 176) define unprivledge loads, which
 # NaCl doesn't allow.
@@ skipping 478 matching lines @@
                     cccc100pu1w1nnnn1rrrrrrrrrrrrrrr
 | 10xxxx    -     = BranchImmediate24 => Branch
                     B_Rule_16_A1_P44
                     cccc1010iiiiiiiiiiiiiiiiiiiiiiii
 | 11xxxx    -     = BranchImmediate24 => Branch
                     Bl_Blx_Rule_23_A1_P58
                     cccc1011iiiiiiiiiiiiiiiiiiiiiiii
 +--
 
 +-- coprocessor_instructions_and_supervisor_call (See Section A5.6)
-# Note: We currently only allow floating point (and advanced SIMD) 
+# Note: We currently only allow floating point (and advanced SIMD)
 # coprocessor operations (coproc=101x).
 # Note: Column op1 is repeated so that the first three rows can define
 # (anded) multiple test conditions for this row.
-| op1(25:20) op(4) coproc(11:8) Rn(19:16) op1_repeated(25:20) 
+| op1(25:20) op(4) coproc(11:8) Rn(19:16) op1_repeated(25:20)
 | 0xxxxx     -     101x         -         ~000x0x
                    -> extension_register_load_store_instructions
 | 0xxxx0     -     ~101x           -      ~000x0x
                    # Note: Never safe since coproc!=101x
                    = Forbidden  # STC A8-372
 | 0xxxx1     -     ~101x        ~1111      ~000x0x
                    # Note: Never safe since coproc!=101x
                    = Forbidden        # LDC(immediate), LDC2(immediate) A8-106
 | "          "     "            1111       -
                    # Note: Never safe since coproc!=101x
@@ skipping 47 matching lines @@
 | "           x1        = CondVfpOp => VfpOp
                           Vsub_Rule_402_A2_P790
                           cccc11100d11nnnndddd101sn1m0mmmm
 | 1x00        x0        = CondVfpOp => VfpOp
                           Vdiv_Rule_301_A1_P590
                           cccc11101d00nnnndddd101sn0m0mmmm
 | 1x11        -         -> other_floating_point_data_processing_instructions
 +--
 
 +-- other_floating_point_data_processing_instructions (A7.5 Table A7-17, page 17-25)
-# Other VPD data-processing, CDP instructions for coprocessors 10/11. 
+# Other VPD data-processing, CDP instructions for coprocessors 10/11.
 #
 # Note: Currently, all instructions use class CoprocessorOp
 # to follow what the previous version of the ARM validator did.
 #
 # TODO(karl): Fix the class decoders to do the right thing.
 | opc2(19:16) opc3(7:6)
 | -           x0        = CondVfpOp => VfpOp
                           Vmov_Rule_326_A2_P640
                           cccc11101d11iiiidddd101s0000iiii
 | 0000        01        = CondVfpOp => VfpOp
@@ skipping 124 matching lines @@
 | C(8) op(7:4)
 | 0    00x1    # TODO(karl): Fix this to do the right thing.
                # VMOV A8-650
                = MoveDoubleFromCoprocessor
 | 1    00x1    # TODO(karl): Fix this to do the right thing.
                # VMOV A8-652
                = MoveDoubleFromCoprocessor
 +--
 
 +-- unconditional_instructions (See Section A5.7)
-# Note: We currently only allow floating point (and advanced SIMD) 
+# Note: We currently only allow floating point (and advanced SIMD)
 # coprocessor operations (coproc=101x).
 #
 # Note: Most instructions in this table are forbidden because they
 # aren't specific to the Vfp coprocessors (10, 11).
 | op1(27:20) op(4) Rn(19:16)
 | 0xxx_xxxx  -     -         ->memory_hints_andvanced_simd_instructions_and_miscellaneous_instructions
 # Note: These instructions are not allowed for any coprocessor.
 | 100x_x1x0  -     -         = ForbiddenUncondNop # SRS B6-20
                              => Forbidden (v6)
 | 100x_x0x1  -     -         = ForbiddenUncondNop # RFE B6-16
@@ skipping 283 matching lines @@
 | "     1001    "
 | "     1101    =VectorLoad  # VLD2(single, all lanes)
 | "     0x10    =VectorLoad  # VLD3(single)
 | "     1010    "
 | "     1110    =VectorLoad  # VLD3(single, all lanes)
 | "     0x11    =VectorLoad  # VLD4(single)
 | "     1011    "
 | "     1111    =VectorLoad  # VLD4(single, all lanes)
 | else:         =Undefined   # Note on page A7-27
 +--