Remove the llvm.nacl.thread.stack.padding intrinsic

lib/Target/X86/X86ISelLowering.cpp

 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 //
 // This file defines the interfaces that X86 uses to lower LLVM code into a
@@ skipping 1229 matching lines @@
   setTargetDAGCombine(ISD::UINT_TO_FP);
   setTargetDAGCombine(ISD::SINT_TO_FP);
   setTargetDAGCombine(ISD::SETCC);
   setTargetDAGCombine(ISD::FP_TO_SINT);
   if (Subtarget->is64Bit())
     setTargetDAGCombine(ISD::MUL);
   setTargetDAGCombine(ISD::XOR);
 
   // @LOCALMOD-BEGIN
   if (Subtarget->isTargetNaCl()) {
-    setOperationAction(ISD::NACL_THREAD_STACK_PADDING, MVT::i32, Custom);
     setOperationAction(ISD::NACL_TP_ALIGN,             MVT::i32, Custom);
     setOperationAction(ISD::NACL_TP_TLS_OFFSET,        MVT::i32, Custom);
     setOperationAction(ISD::NACL_TP_TDB_OFFSET,        MVT::i32, Custom);
     setOperationAction(ISD::NACL_TARGET_ARCH,          MVT::i32, Custom);
   }
   // @LOCALMOD-END
 
   computeRegisterProperties();
 
   // On Darwin, -Os means optimize for size without hurting performance,
@@ skipping 8325 matching lines @@
 
 SDValue X86TargetLowering::LowerNaClTpTdbOffset(SDValue Op,
                                                 SelectionDAG &DAG) const {
   // ssize_t __nacl_tp_tdb_offset (size_t tdb_size) {
   //   return 0;
   // }
   return DAG.getConstant(0, Op.getValueType().getSimpleVT());
 }
 
 SDValue
-X86TargetLowering::LowerNaClThreadStackPadding(SDValue Op,
-                                               SelectionDAG &DAG) const {
-  // size_t __nacl_thread_stack_padding () {
-  //   return reg_size;
-  // }
-  return DAG.getConstant(RegInfo->getSlotSize(),
-                         Op.getValueType().getSimpleVT());
-}
-
-SDValue
 X86TargetLowering::LowerNaClTargetArch(SDValue Op, SelectionDAG &DAG) const {
   // int __nacl_target_arch () {
   //   return (is_64_bit ?
   //           PnaclTargetArchitectureX86_64 :
   //           PnaclTargetArchitectureX86_32);
   // }
   return DAG.getConstant((Subtarget->is64Bit() ?
                           PnaclTargetArchitectureX86_64 :
                           PnaclTargetArchitectureX86_32),
                          Op.getValueType().getSimpleVT());
@@ skipping 1503 matching lines @@
   case ISD::UMULO:              return LowerXALUO(Op, DAG);
   case ISD::READCYCLECOUNTER:   return LowerREADCYCLECOUNTER(Op, DAG);
   case ISD::BITCAST:            return LowerBITCAST(Op, DAG);
   case ISD::ADDC:
   case ISD::ADDE:
   case ISD::SUBC:
   case ISD::SUBE:               return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
   case ISD::ADD:                return LowerADD(Op, DAG);
   case ISD::SUB:                return LowerSUB(Op, DAG);
   // @LOCALMOD-BEGIN
-  case ISD::NACL_THREAD_STACK_PADDING:
-    return LowerNaClThreadStackPadding(Op, DAG);
   case ISD::NACL_TP_ALIGN:         return LowerNaClTpAlign(Op, DAG);
   case ISD::NACL_TP_TLS_OFFSET:    return LowerNaClTpTlsOffset(Op, DAG);
   case ISD::NACL_TP_TDB_OFFSET:    return LowerNaClTpTdbOffset(Op, DAG);
   case ISD::NACL_TARGET_ARCH:      return LowerNaClTargetArch(Op, DAG);
   // @LOCALMOD-END
   }
 }
 
 static void ReplaceATOMIC_LOAD(SDNode *Node,
                                   SmallVectorImpl<SDValue> &Results,
@@ skipping 5163 matching lines @@
     else if (VT == MVT::f64 || VT == MVT::i64)
       Res.second = &X86::FR64RegClass;
     else if (X86::VR128RegClass.hasType(VT))
       Res.second = &X86::VR128RegClass;
     else if (X86::VR256RegClass.hasType(VT))
       Res.second = &X86::VR256RegClass;
   }
 
   return Res;
 }