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Side by Side Diff: lib/Target/Mips/MipsISelLowering.h

Issue 10874034: Remove the llvm.nacl.thread.stack.padding intrinsic (Closed) Base URL: http://git.chromium.org/native_client/pnacl-llvm.git@master
Patch Set: Created 8 years, 4 months ago
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1 //===-- MipsISelLowering.h - Mips DAG Lowering Interface --------*- C++ -*-===// 1 //===-- MipsISelLowering.h - Mips DAG Lowering Interface --------*- C++ -*-===//
2 // 2 //
3 // The LLVM Compiler Infrastructure 3 // The LLVM Compiler Infrastructure
4 // 4 //
5 // This file is distributed under the University of Illinois Open Source 5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details. 6 // License. See LICENSE.TXT for details.
7 // 7 //
8 //===----------------------------------------------------------------------===// 8 //===----------------------------------------------------------------------===//
9 // 9 //
10 // This file defines the interfaces that Mips uses to lower LLVM code into a 10 // This file defines the interfaces that Mips uses to lower LLVM code into a
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145 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const; 145 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
146 SDValue LowerMEMBARRIER(SDValue Op, SelectionDAG& DAG) const; 146 SDValue LowerMEMBARRIER(SDValue Op, SelectionDAG& DAG) const;
147 SDValue LowerATOMIC_FENCE(SDValue Op, SelectionDAG& DAG) const; 147 SDValue LowerATOMIC_FENCE(SDValue Op, SelectionDAG& DAG) const;
148 SDValue LowerShiftLeftParts(SDValue Op, SelectionDAG& DAG) const; 148 SDValue LowerShiftLeftParts(SDValue Op, SelectionDAG& DAG) const;
149 SDValue LowerShiftRightParts(SDValue Op, SelectionDAG& DAG, 149 SDValue LowerShiftRightParts(SDValue Op, SelectionDAG& DAG,
150 bool IsSRA) const; 150 bool IsSRA) const;
151 SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const; 151 SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const;
152 SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const; 152 SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const;
153 153
154 // @LOCALMOD-BEGIN 154 // @LOCALMOD-BEGIN
155 SDValue LowerNaClThreadStackPadding(SDValue Op, SelectionDAG &DAG) const;
156 SDValue LowerNaClTpAlign(SDValue Op, SelectionDAG &DAG) const; 155 SDValue LowerNaClTpAlign(SDValue Op, SelectionDAG &DAG) const;
157 SDValue LowerNaClTpTlsOffset(SDValue Op, SelectionDAG &DAG) const; 156 SDValue LowerNaClTpTlsOffset(SDValue Op, SelectionDAG &DAG) const;
158 SDValue LowerNaClTpTdbOffset(SDValue Op, SelectionDAG &DAG) const; 157 SDValue LowerNaClTpTdbOffset(SDValue Op, SelectionDAG &DAG) const;
159 // @LOCALMOD-END 158 // @LOCALMOD-END
160 159
161 virtual SDValue 160 virtual SDValue
162 LowerFormalArguments(SDValue Chain, 161 LowerFormalArguments(SDValue Chain,
163 CallingConv::ID CallConv, bool isVarArg, 162 CallingConv::ID CallConv, bool isVarArg,
164 const SmallVectorImpl<ISD::InputArg> &Ins, 163 const SmallVectorImpl<ISD::InputArg> &Ins,
165 DebugLoc dl, SelectionDAG &DAG, 164 DebugLoc dl, SelectionDAG &DAG,
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221 MachineBasicBlock *BB, unsigned Size, unsigned BinOpcode, 220 MachineBasicBlock *BB, unsigned Size, unsigned BinOpcode,
222 bool Nand = false) const; 221 bool Nand = false) const;
223 MachineBasicBlock *EmitAtomicCmpSwap(MachineInstr *MI, 222 MachineBasicBlock *EmitAtomicCmpSwap(MachineInstr *MI,
224 MachineBasicBlock *BB, unsigned Size) const; 223 MachineBasicBlock *BB, unsigned Size) const;
225 MachineBasicBlock *EmitAtomicCmpSwapPartword(MachineInstr *MI, 224 MachineBasicBlock *EmitAtomicCmpSwapPartword(MachineInstr *MI,
226 MachineBasicBlock *BB, unsigned Size) const; 225 MachineBasicBlock *BB, unsigned Size) const;
227 }; 226 };
228 } 227 }
229 228
230 #endif // MipsISELLOWERING_H 229 #endif // MipsISELLOWERING_H
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