Refactor Math.min/max to be a single HInstruction.

src/arm/disasm-arm.cc

Index: src/arm/disasm-arm.cc
diff --git a/src/arm/disasm-arm.cc b/src/arm/disasm-arm.cc
index 96a7d3ce6b6dfbc1d4c8bdf64e5ee53c9ba709ad..b03207cacbce3df67ecfe155e3259226c03308c1 100644
--- a/src/arm/disasm-arm.cc
+++ b/src/arm/disasm-arm.cc
@@ -131,6 +131,7 @@ class Decoder {
   int DecodeType7(Instruction* instr);
   // For VFP support.
   void DecodeTypeVFP(Instruction* instr);
+  void DecodeSpecialCondition(Instruction* instr);
   void DecodeType6CoprocessorIns(Instruction* instr);
 
   void DecodeVMOVBetweenCoreAndSinglePrecisionRegisters(Instruction* instr);
@@ -1211,6 +1212,22 @@ void Decoder::DecodeVCMP(Instruction* instr) {
 }
 
 
+// Currently supports:
+// Dd = vorr(Dn, Dm)
+void Decoder::DecodeSpecialCondition(Instruction* instr) {
+  // See ARM DDI 0406A, A7-12 for how to detect which instruction this is.
+  if (instr->Bits(11, 8) == 0x1 &&
+      instr->Bit(4) == 0x1 &&
+      instr->Bit(24) == 0x0 &&
+      instr->Opc1Value() == 0x2) {

[Erik Corry, 2012/08/06 10:44:40]

This tests bits 20, 21, 23, 24, but ignores bits 25-27 and 22 and 4-7.  Should
it not say 'Unknown' if they do not match the expectations for vorr?

[Jakob Kummerow, 2012/08/06 14:08:43]

As discussed, removed vorr completely.

+    // vorr
+    Format(instr, "vorr 'Dd, 'Dn, 'Dm");
+  } else {
+    Unknown(instr);
+  }
+}
+
+
 void Decoder::DecodeVCVTBetweenDoubleAndSingle(Instruction* instr) {
   VERIFY((instr->Bit(4) == 0) && (instr->Opc1Value() == 0x7));
   VERIFY((instr->Opc2Value() == 0x7) && (instr->Opc3Value() == 0x3));
@@ -1382,7 +1399,7 @@ int Decoder::InstructionDecode(byte* instr_ptr) {
                                   "%08x       ",
                                   instr->InstructionBits());
   if (instr->ConditionField() == kSpecialCondition) {
-    Unknown(instr);
+    DecodeSpecialCondition(instr);
     return Instruction::kInstrSize;
   }
   int instruction_bits = *(reinterpret_cast<int*>(instr_ptr));