Define a baseline and testing patterns for ARM load_store_word_byte table.

src/trusted/validator_arm/gen/arm32_decode.cc

Index: src/trusted/validator_arm/gen/arm32_decode.cc
===================================================================
--- src/trusted/validator_arm/gen/arm32_decode.cc	(revision 8812)
+++ src/trusted/validator_arm/gen/arm32_decode.cc	(working copy)
@@ -42,9 +42,7 @@
   , LoadCoprocessor_instance_()
   , LoadDoubleExclusive_instance_()
   , LoadExclusive_instance_()
-  , LoadImmediate_instance_()
   , LoadMultiple_instance_()
-  , LoadRegister_instance_()
   , LongMultiply_instance_()
   , MaskAddress_instance_()
   , MoveDoubleFromCoprocessor_instance_()
@@ -57,7 +55,6 @@
   , StoreCoprocessor_instance_()
   , StoreExclusive_instance_()
   , StoreImmediate_instance_()
-  , StoreRegister_instance_()
   , StrImmediate_instance_()
   , StrImmediateDouble_instance_()
   , StrRegister_instance_()
@@ -464,22 +461,22 @@
   if ((insn.Bits() & 0x02000000) == 0x00000000 /* A(25:25) == 0 */ &&
       (insn.Bits() & 0x01300000) == 0x00000000 /* op1(24:20) == 0xx00 */ &&
       true)
-    return StoreImmediate_instance_;
+    return StrImmediate_instance_;
 
   if ((insn.Bits() & 0x02000000) == 0x00000000 /* A(25:25) == 0 */ &&
       (insn.Bits() & 0x01300000) == 0x00100000 /* op1(24:20) == 0xx01 */ &&
       true)
-    return LoadImmediate_instance_;
+    return LdrImmediate_instance_;
 
   if ((insn.Bits() & 0x02000000) == 0x00000000 /* A(25:25) == 0 */ &&
       (insn.Bits() & 0x01100000) == 0x01000000 /* op1(24:20) == 1xxx0 */ &&
       true)
-    return StoreImmediate_instance_;
+    return StrImmediate_instance_;
 
   if ((insn.Bits() & 0x02000000) == 0x00000000 /* A(25:25) == 0 */ &&
       (insn.Bits() & 0x01100000) == 0x01100000 /* op1(24:20) == 1xxx1 */ &&
       true)
-    return LoadImmediate_instance_;
+    return LdrImmediate_instance_;
 
   if ((insn.Bits() & 0x02000000) == 0x00000000 /* A(25:25) == 0 */ &&
       (insn.Bits() & 0x01200000) == 0x00200000 /* op1(24:20) == 0xx1x */ &&
@@ -489,27 +486,27 @@
   if ((insn.Bits() & 0x02000000) == 0x02000000 /* A(25:25) == 1 */ &&
       (insn.Bits() & 0x01700000) == 0x00500000 /* op1(24:20) == 0x101 */ &&
       (insn.Bits() & 0x00000010) == 0x00000000 /* B(4:4) == 0 */)
-    return LoadRegister_instance_;
+    return LdrRegister_instance_;
 
   if ((insn.Bits() & 0x02000000) == 0x02000000 /* A(25:25) == 1 */ &&
       (insn.Bits() & 0x00700000) == 0x00100000 /* op1(24:20) == xx001 */ &&
       (insn.Bits() & 0x00000010) == 0x00000000 /* B(4:4) == 0 */)
-    return LoadRegister_instance_;
+    return LdrRegister_instance_;
 
   if ((insn.Bits() & 0x02000000) == 0x02000000 /* A(25:25) == 1 */ &&
       (insn.Bits() & 0x01300000) == 0x00000000 /* op1(24:20) == 0xx00 */ &&
       (insn.Bits() & 0x00000010) == 0x00000000 /* B(4:4) == 0 */)
-    return StoreRegister_instance_;
+    return StrRegister_instance_;
 
   if ((insn.Bits() & 0x02000000) == 0x02000000 /* A(25:25) == 1 */ &&
       (insn.Bits() & 0x01100000) == 0x01000000 /* op1(24:20) == 1xxx0 */ &&
       (insn.Bits() & 0x00000010) == 0x00000000 /* B(4:4) == 0 */)
-    return StoreRegister_instance_;
+    return StrRegister_instance_;
 
   if ((insn.Bits() & 0x02000000) == 0x02000000 /* A(25:25) == 1 */ &&
       (insn.Bits() & 0x01100000) == 0x01100000 /* op1(24:20) == 1xxx1 */ &&
       (insn.Bits() & 0x00000010) == 0x00000000 /* B(4:4) == 0 */)
-    return LoadRegister_instance_;
+    return LdrRegister_instance_;
 
   if ((insn.Bits() & 0x02000000) == 0x02000000 /* A(25:25) == 1 */ &&
       (insn.Bits() & 0x01200000) == 0x00200000 /* op1(24:20) == 0xx1x */ &&