Define a baseline and testing patterns for ARM load_store_word_byte table.

src/trusted/validator_arm/inst_classes_testers.cc

 /*
  * Copyright (c) 2012 The Native Client Authors. All rights reserved.
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 #ifndef NACL_TRUSTED_BUT_NOT_TCB
 #error This file is not meant for use in the TCB
 #endif
 
 #include "native_client/src/trusted/validator_arm/inst_classes_testers.h"
@@ skipping 726 matching lines @@
   EXPECT_FALSE(expected_decoder.d_lo.reg(inst).Equals(kRegisterPc))
       << "Expected Unpredictable for " << InstContents();
   EXPECT_FALSE(expected_decoder.m.reg(inst).Equals(kRegisterPc))
       << "Expected Unpredictable for " << InstContents();
   EXPECT_FALSE(expected_decoder.n.reg(inst).Equals(kRegisterPc))
       << "Expected Unpredictable for " << InstContents();
 
   return true;
 }
 
-// LoadStore2RegisterImmediateOpTester
-LoadStore2RegisterImmediateOpTester::LoadStore2RegisterImmediateOpTester(
+// LoadStore2RegisterImm8OpTester
+LoadStore2RegisterImm8OpTester::LoadStore2RegisterImm8OpTester(
     const NamedClassDecoder& decoder) : Arm32DecoderTester(decoder) {}
 
-bool LoadStore2RegisterImmediateOpTester::
+bool LoadStore2RegisterImm8OpTester::
 ApplySanityChecks(Instruction inst,
                   const NamedClassDecoder& decoder) {
-  nacl_arm_dec::LoadStore2RegisterImmediateOp expected_decoder;
+  nacl_arm_dec::LoadStore2RegisterImm8Op expected_decoder;
   // Check that condition is defined correctly.
   EXPECT_EQ(expected_decoder.cond.value(inst), inst.Bits(31, 28));
 
   // Didn't parse undefined conditional.
   if (expected_decoder.cond.undefined(inst)) {
     NC_EXPECT_NE_PRECOND(&ExpectedDecoder(), &decoder);
   }
 
   // Should not parse if P=0 && W=1.
   if (expected_decoder.indexing.IsPostIndexing(inst) &&
       expected_decoder.writes.IsDefined(inst)) {
     NC_EXPECT_NE_PRECOND(&ExpectedDecoder(), &decoder);
   }
 
   // Check if expected class name found.
   NC_PRECOND(Arm32DecoderTester::ApplySanityChecks(inst, decoder));
 
   // Check Registers and flags used.
   EXPECT_TRUE(expected_decoder.t.reg(inst).Equals(inst.Reg(15, 12)));
   EXPECT_TRUE(expected_decoder.n.reg(inst).Equals(inst.Reg(19, 16)));
   EXPECT_EQ(expected_decoder.writes.IsDefined(inst), inst.Bit(21));
   EXPECT_EQ(expected_decoder.direction.IsAdd(inst), inst.Bit(23));
   EXPECT_EQ(expected_decoder.indexing.IsPreIndexing(inst), inst.Bit(24));
 
   // Other ARM constraints about this instruction.
   EXPECT_FALSE(expected_decoder.t.reg(inst).Equals(kRegisterPc))
       << "Expected UNPREDICTABLE for " << InstContents();
 
-  EXPECT_FALSE(expected_decoder.HasWriteBack(inst) &&
-               (expected_decoder.n.reg(inst).Equals(kRegisterPc) ||
-                expected_decoder.n.reg(inst).Equals(
-                    expected_decoder.t.reg(inst))))
-      << "Expected UNPREDICTABLE for " << InstContents();
+  // NOTE: The manual states that that it is also unpredictable
+  // when HasWriteBack(i) and Rn=Rt. However, the compilers
+  // may not check for this. For the moment, we are changing
+  // the code to ignore this case for loads and store.
+  // TODO(karl): Should we not allow this?
+  // EXPECT_FALSE(expected_decoder.HasWriteBack(inst) &&
+  //              (expected_decoder.n.reg(inst).Equals(kRegisterPc) ||
+  //               expected_decoder.n.reg(inst).Equals(
+  //                   expected_decoder.t.reg(inst))))
+  //     << "Expected UNPREDICTABLE for " << InstContents();
 
   // Other NaCl constraints about this instruction.
   EXPECT_FALSE(ExpectedDecoder().defs(inst).Contains(kRegisterPc))
       << "Expected FORBIDDEN_OPERANDS for " << InstContents();
 
   return true;
 }
 
-// LoadStore2RegisterImmediateOpTesterNotRnIsPc
-LoadStore2RegisterImmediateOpTesterNotRnIsPc::
-LoadStore2RegisterImmediateOpTesterNotRnIsPc(
+// LoadStore2RegisterImm8OpTesterNotRnIsPc
+LoadStore2RegisterImm8OpTesterNotRnIsPc::
+LoadStore2RegisterImm8OpTesterNotRnIsPc(
     const NamedClassDecoder& decoder)
-    : LoadStore2RegisterImmediateOpTester(decoder) {}
+    : LoadStore2RegisterImm8OpTester(decoder) {}
 
-bool LoadStore2RegisterImmediateOpTesterNotRnIsPc::
+bool LoadStore2RegisterImm8OpTesterNotRnIsPc::
 ApplySanityChecks(Instruction inst,
                   const NamedClassDecoder& decoder) {
-  nacl_arm_dec::LoadStore2RegisterImmediateOp expected_decoder;
+  nacl_arm_dec::LoadStore2RegisterImm8Op expected_decoder;
 
   // Check that we don't parse when Rn=15.
   if (expected_decoder.n.reg(inst).Equals(kRegisterPc)) {
     NC_EXPECT_NE_PRECOND(&ExpectedDecoder(), &decoder);
   }
 
-  return LoadStore2RegisterImmediateOpTester::ApplySanityChecks(inst, decoder);
+  return LoadStore2RegisterImm8OpTester::ApplySanityChecks(inst, decoder);
 }
 
-// LoadStore2RegisterImmediateDoubleOpTester
-LoadStore2RegisterImmediateDoubleOpTester::
-LoadStore2RegisterImmediateDoubleOpTester(const NamedClassDecoder& decoder)
-    : LoadStore2RegisterImmediateOpTester(decoder) {}
+// LoadStore2RegisterImm8DoubleOpTester
+LoadStore2RegisterImm8DoubleOpTester::
+LoadStore2RegisterImm8DoubleOpTester(const NamedClassDecoder& decoder)
+    : LoadStore2RegisterImm8OpTester(decoder) {}
 
-bool LoadStore2RegisterImmediateDoubleOpTester::
+bool LoadStore2RegisterImm8DoubleOpTester::
 ApplySanityChecks(Instruction inst,
                   const NamedClassDecoder& decoder) {
-  NC_PRECOND(LoadStore2RegisterImmediateOpTester::
+  NC_PRECOND(LoadStore2RegisterImm8OpTester::
              ApplySanityChecks(inst, decoder));
 
   // Check Registers and flags used.
-  nacl_arm_dec::LoadStore2RegisterImmediateDoubleOp expected_decoder;
+  nacl_arm_dec::LoadStore2RegisterImm8DoubleOp expected_decoder;
   EXPECT_EQ(expected_decoder.t.number(inst) + 1,
             expected_decoder.t2.number(inst));
 
   // Other ARM constraints about this instruction.
   EXPECT_TRUE(expected_decoder.t.IsEven(inst));
   EXPECT_NE(expected_decoder.t2.number(inst), static_cast<uint32_t>(15))
       << "Expected UNPREDICTABLE for " << InstContents();
-  EXPECT_FALSE(expected_decoder.HasWriteBack(inst) &&
-               expected_decoder.n.reg(inst).Equals(
-                   expected_decoder.t2.reg(inst)))
-      << "Expected UNPREDICTABLE for " << InstContents();
+
+  // NOTE: The manual states that that it is also unpredictable
+  // when HasWriteBack(i) and Rn=Rt. However, the compilers
+  // may not check for this. For the moment, we are changing
+  // the code to ignore this case for loads and store.
+  // TODO(karl): Should we not allow this?
+  // EXPECT_FALSE(expected_decoder.HasWriteBack(inst) &&
+  //              expected_decoder.n.reg(inst).Equals(
+  //                  expected_decoder.t2.reg(inst)))
+  //     << "Expected UNPREDICTABLE for " << InstContents();
 
   return true;
 }
 
-// LoadStore2RegisterImmediateDoubleOpTesterNotRnIsPc
-LoadStore2RegisterImmediateDoubleOpTesterNotRnIsPc::
-LoadStore2RegisterImmediateDoubleOpTesterNotRnIsPc(
+// LoadStore2RegisterImm8DoubleOpTesterNotRnIsPc
+LoadStore2RegisterImm8DoubleOpTesterNotRnIsPc::
+LoadStore2RegisterImm8DoubleOpTesterNotRnIsPc(
     const NamedClassDecoder& decoder)
-    : LoadStore2RegisterImmediateDoubleOpTester(decoder) {}
+    : LoadStore2RegisterImm8DoubleOpTester(decoder) {}
 
-bool LoadStore2RegisterImmediateDoubleOpTesterNotRnIsPc::
+bool LoadStore2RegisterImm8DoubleOpTesterNotRnIsPc::
 ApplySanityChecks(Instruction inst,
                   const NamedClassDecoder& decoder) {
-  nacl_arm_dec::LoadStore2RegisterImmediateDoubleOp expected_decoder;
+  nacl_arm_dec::LoadStore2RegisterImm8DoubleOp expected_decoder;
 
   // Check that we don't parse when Rn=15.
   if (expected_decoder.n.reg(inst).Equals(kRegisterPc)) {
     NC_EXPECT_NE_PRECOND(&ExpectedDecoder(), &decoder);
   }
 
-  return LoadStore2RegisterImmediateDoubleOpTester::
+  return LoadStore2RegisterImm8DoubleOpTester::
       ApplySanityChecks(inst, decoder);
 }
 
+// LoadStore2RegisterImm12OpTester
+LoadStore2RegisterImm12OpTester::LoadStore2RegisterImm12OpTester(
+    const NamedClassDecoder& decoder) : Arm32DecoderTester(decoder) {}
+
+bool LoadStore2RegisterImm12OpTester::
+ApplySanityChecks(Instruction inst,
+                  const NamedClassDecoder& decoder) {
+  nacl_arm_dec::LoadStore2RegisterImm12Op expected_decoder;
+  // Check that condition is defined correctly.
+  EXPECT_EQ(expected_decoder.cond.value(inst), inst.Bits(31, 28));
+
+  // Didn't parse undefined conditional.
+  if (expected_decoder.cond.undefined(inst)) {
+    NC_EXPECT_NE_PRECOND(&ExpectedDecoder(), &decoder);
+  }
+
+  // Should not parse if P=0 && W=1.
+  if (expected_decoder.indexing.IsPostIndexing(inst) &&
+      expected_decoder.writes.IsDefined(inst)) {
+    NC_EXPECT_NE_PRECOND(&ExpectedDecoder(), &decoder);
+  }
+
+  // Check if expected class name found.
+  NC_PRECOND(Arm32DecoderTester::ApplySanityChecks(inst, decoder));
+
+  // Check Registers and flags used.
+  EXPECT_EQ(expected_decoder.imm12.value(inst), inst.Bits(11, 0));
+  EXPECT_TRUE(expected_decoder.t.reg(inst).Equals(inst.Reg(15, 12)));
+  EXPECT_TRUE(expected_decoder.n.reg(inst).Equals(inst.Reg(19, 16)));
+  EXPECT_EQ(expected_decoder.writes.IsDefined(inst), inst.Bit(21));
+  EXPECT_EQ(expected_decoder.direction.IsAdd(inst), inst.Bit(23));
+  EXPECT_EQ(expected_decoder.indexing.IsPreIndexing(inst), inst.Bit(24));
+
+  // Other ARM constraints about this instruction.
+  EXPECT_FALSE(expected_decoder.t.reg(inst).Equals(kRegisterPc))
+      << "Expected UNPREDICTABLE for " << InstContents();
+
+  // NOTE: The manual states that that it is also unpredictable
+  // when HasWriteBack(i) and Rn=Rt. However, the compilers
+  // may not check for this. For the moment, we are changing
+  // the code to ignore this case for loads and store.
+  // TODO(karl): Should we not allow this?
+  // EXPECT_FALSE(expected_decoder.HasWriteBack(inst) &&
+  //              (expected_decoder.n.reg(inst).Equals(kRegisterPc) ||
+  //               expected_decoder.n.reg(inst).Equals(
+  //                   expected_decoder.t.reg(inst))))
+  //     << "Expected UNPREDICTABLE for " << InstContents();
+
+  // Other NaCl constraints about this instruction.
+  EXPECT_FALSE(ExpectedDecoder().defs(inst).Contains(kRegisterPc))
+      << "Expected FORBIDDEN_OPERANDS for " << InstContents();
+
+  return true;
+}
+
+// LoadStore2RegisterImm12OpTesterNotRnIsPc
+LoadStore2RegisterImm12OpTesterNotRnIsPc::
+LoadStore2RegisterImm12OpTesterNotRnIsPc(
+    const NamedClassDecoder& decoder)
+    : LoadStore2RegisterImm12OpTester(decoder) {}
+
+bool LoadStore2RegisterImm12OpTesterNotRnIsPc::
+ApplySanityChecks(Instruction inst,
+                  const NamedClassDecoder& decoder) {
+  nacl_arm_dec::LoadStore2RegisterImm12Op expected_decoder;
+
+  // Check that we don't parse when Rn=15.
+  if (expected_decoder.n.reg(inst).Equals(kRegisterPc)) {
+    NC_EXPECT_NE_PRECOND(&ExpectedDecoder(), &decoder);
+  }
+
+  return LoadStore2RegisterImm12OpTester::ApplySanityChecks(inst, decoder);
+}
+
+
 // LoadStore3RegisterOpTester
 LoadStore3RegisterOpTester::LoadStore3RegisterOpTester(
     const NamedClassDecoder& decoder) : Arm32DecoderTester(decoder) {}
 
 bool LoadStore3RegisterOpTester::
 ApplySanityChecks(Instruction inst,
                   const NamedClassDecoder& decoder) {
   nacl_arm_dec::LoadStore3RegisterOp expected_decoder;
 
   // Check that condition is defined correctly.
@@ skipping 19 matching lines @@
   EXPECT_TRUE(expected_decoder.n.reg(inst).Equals(inst.Reg(19, 16)));
   EXPECT_EQ(expected_decoder.writes.IsDefined(inst), inst.Bit(21));
   EXPECT_EQ(expected_decoder.direction.IsAdd(inst), inst.Bit(23));
   EXPECT_EQ(expected_decoder.indexing.IsPreIndexing(inst), inst.Bit(24));
 
   // Other ARM constraints about this instruction.
   EXPECT_FALSE(expected_decoder.n.reg(inst).Equals(kRegisterPc))
       << "Expected UNPREDICTABLE for " << InstContents();
   EXPECT_FALSE(expected_decoder.t.reg(inst).Equals(kRegisterPc))
       << "Expected UNPREDICTABLE for " << InstContents();
-  EXPECT_FALSE(expected_decoder.HasWriteBack(inst) &&
-               (expected_decoder.n.reg(inst).Equals(kRegisterPc) ||
-                expected_decoder.n.reg(inst).Equals(
-                    expected_decoder.t.reg(inst))))
-      << "Expected UNPREDICTABLE for " << InstContents();
+
+  // NOTE: The manual states that that it is also unpredictable
+  // when HasWriteBack(i) and Rn=Rt. However, the compilers
+  // may not check for this. For the moment, we are changing
+  // the code to ignore this case for loads and stores.
+  // TODO(karl): Should we not allow this?
+  // EXPECT_FALSE(expected_decoder.HasWriteBack(inst) &&
+  //              (expected_decoder.n.reg(inst).Equals(kRegisterPc) ||
+  //               expected_decoder.n.reg(inst).Equals(
+  //                   expected_decoder.t.reg(inst))))
+  //     << "Expected UNPREDICTABLE for " << InstContents();
 
   // Other NaCl constraints about this instruction.
   EXPECT_FALSE(expected_decoder.indexing.IsPreIndexing(inst))
       << "Expected FORBIDDEN for " << InstContents();
 
   EXPECT_FALSE(ExpectedDecoder().defs(inst).Contains(kRegisterPc))
       << "Expected FORBIDDEN_OPERANDS for " << InstContents();
 
   return true;
 }
@@ skipping 11 matching lines @@
 
   // Check Registers and flags used.
   nacl_arm_dec::LoadStore3RegisterDoubleOp expected_decoder;
   EXPECT_EQ(expected_decoder.t.number(inst) + 1,
             expected_decoder.t2.number(inst));
 
   // Other ARM constraints about this instruction.
   EXPECT_TRUE(expected_decoder.t.IsEven(inst));
   EXPECT_NE(expected_decoder.t2.number(inst), static_cast<uint32_t>(15))
       << "Expected UNPREDICTABLE for " << InstContents();
-  EXPECT_FALSE(expected_decoder.HasWriteBack(inst) &&
-               expected_decoder.n.reg(inst).Equals(
-                   expected_decoder.t2.reg(inst)))
-      << "Expected UNPREDICTABLE for " << InstContents();
+
+  // NOTE: The manual states that that it is also unpredictable
+  // when HasWriteBack(i) and Rn=Rt. However, the compilers
+  // may not check for this. For the moment, we are changing
+  // the code to ignore this case for loads and stores.
+  // TODO(karl): Should we not allow this?
+  // EXPECT_FALSE(expected_decoder.HasWriteBack(inst) &&
+  //              expected_decoder.n.reg(inst).Equals(
+  //                  expected_decoder.t2.reg(inst)))
+  //     << "Expected UNPREDICTABLE for " << InstContents();
 
   return true;
 }
 
+// LoadStore3RegisterImm5OpTester
+LoadStore3RegisterImm5OpTester::LoadStore3RegisterImm5OpTester(
+    const NamedClassDecoder& decoder) : Arm32DecoderTester(decoder) {}
+
+bool LoadStore3RegisterImm5OpTester::
+ApplySanityChecks(Instruction inst,
+                  const NamedClassDecoder& decoder) {
+  nacl_arm_dec::LoadStore3RegisterImm5Op expected_decoder;
+  // Check that condition is defined correctly.
+  EXPECT_EQ(expected_decoder.cond.value(inst), inst.Bits(31, 28));
+
+  // Didn't parse undefined conditional.
+  if (expected_decoder.cond.undefined(inst)) {
+    NC_EXPECT_NE_PRECOND(&ExpectedDecoder(), &decoder);
+  }
+
+  // Should not parse if P=0 && W=1.
+  if (expected_decoder.indexing.IsPostIndexing(inst) &&
+      expected_decoder.writes.IsDefined(inst)) {
+    NC_EXPECT_NE_PRECOND(&ExpectedDecoder(), &decoder);
+  }
+
+  // Check if expected class name found.
+  NC_PRECOND(Arm32DecoderTester::ApplySanityChecks(inst, decoder));
+
+  // Check Registers and flags used.
+  EXPECT_TRUE(expected_decoder.m.reg(inst).Equals(inst.Reg(3, 0)));
+  EXPECT_TRUE(expected_decoder.t.reg(inst).Equals(inst.Reg(15, 12)));
+  EXPECT_TRUE(expected_decoder.n.reg(inst).Equals(inst.Reg(19, 16)));
+  EXPECT_EQ(expected_decoder.writes.IsDefined(inst), inst.Bit(21));
+  EXPECT_EQ(expected_decoder.direction.IsAdd(inst), inst.Bit(23));
+  EXPECT_EQ(expected_decoder.indexing.IsPreIndexing(inst), inst.Bit(24));
+
+  // Check that immediate value is computed correctly.
+  EXPECT_EQ(expected_decoder.imm.value(inst), inst.Bits(11, 7));
+  EXPECT_EQ(expected_decoder.shift_type.value(inst), inst.Bits(6, 5));
+
+  // Other ARM constraints about this instruction.
+  EXPECT_FALSE(expected_decoder.t.reg(inst).Equals(kRegisterPc))
+      << "Expected UNPREDICTABLE for " << InstContents();
+
+  // NOTE: The manual states that that it is also unpredictable
+  // when HasWriteBack(i) and Rn=Rt. However, the compilers
+  // may not check for this. For the moment, we are changing
+  // the code to ignore this case for loads and store.
+  // TODO(karl): Should we not allow this?
+  // EXPECT_FALSE(expected_decoder.HasWriteBack(inst) &&
+  //              (expected_decoder.n.reg(inst).Equals(kRegisterPc) ||
+  //               expected_decoder.n.reg(inst).Equals(
+  //                   expected_decoder.t.reg(inst))))
+  //     << "Expected UNPREDICTABLE for " << InstContents();
+
+  // Other NaCl constraints about this instruction.
+  EXPECT_FALSE(ExpectedDecoder().defs(inst).Contains(kRegisterPc))
+      << "Expected FORBIDDEN_OPERANDS for " << InstContents();
+
+  return true;
+}
+
 // Unary2RegisterImmedShiftedOpTester
 Unary2RegisterImmedShiftedOpTester::Unary2RegisterImmedShiftedOpTester(
     const NamedClassDecoder& decoder)
     : Arm32DecoderTester(decoder) {}
 
 bool Unary2RegisterImmedShiftedOpTester::
 ApplySanityChecks(Instruction inst,
                   const NamedClassDecoder& decoder) {
   nacl_arm_dec::Unary2RegisterImmedShiftedOp expected_decoder;
 
@@ skipping 373 matching lines @@
       << "Expected Unpredictable for " << InstContents();
   EXPECT_FALSE(expected_decoder.s.reg(inst).Equals(kRegisterPc))
       << "Expected Unpredictable for " << InstContents();
   EXPECT_FALSE(expected_decoder.m.reg(inst).Equals(kRegisterPc))
       << "Expected Unpredictable for " << InstContents();
 
   return true;
 }
 
 }  // namespace