Define a baseline and testing patterns for ARM load_store_word_byte table.

src/trusted/validator_arm/actual_classes.cc

 /*
  * Copyright (c) 2012 The Native Client Authors. All rights reserved.
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 #include "native_client/src/trusted/validator_arm/actual_classes.h"
 
 #include <assert.h>
 #include <string.h>
@@ skipping 251 matching lines @@
 }
 
 
 SafetyLevel StrImmediate::safety(const Instruction i) const {
   // Arm restrictions for this instruction.
   if (t.reg(i).Equals(kRegisterPc)) {
     return UNPREDICTABLE;
   }
 
   if (HasWriteBack(i) &&
-      (n.reg(i).Equals(kRegisterPc) || n.reg(i).Equals(t.reg(i)))) {
+      (n.reg(i).Equals(kRegisterPc))) {
+    // NOTE: The manual states that that it is also unpredictable
+    // when HasWriteBack(i) and Rn=Rt. However, the compilers
+    // may not check for this. For the moment, we are changing
+    // the code to ignore this case for stores.
+    // TODO(karl): Should we not allow this?
     return UNPREDICTABLE;
   }
 
   // Don't let addressing writeback alter PC (NaCl constraint).
   if (defs(i).Contains(kRegisterPc)) return FORBIDDEN_OPERANDS;
 
   return MAY_BE_SAFE;
 }
 
 SafetyLevel StrImmediateDouble::safety(const Instruction i) const {
   // Arm double width restrictions for this instruction.
   if (!t.IsEven(i)) {
     return UNDEFINED;
   }
 
   if (t2.reg(i).Equals(kRegisterPc)) {
     return UNPREDICTABLE;
   }
 
-  if (HasWriteBack(i) && n.reg(i).Equals(t2.reg(i))) {
-    return UNPREDICTABLE;
-  }
+  // NOTE: The manual states that that it is also unpredictable
+  // when HasWriteBack(i) and Rn=Rt. However, the compilers
+  // may not check for this. For the moment, we are changing
+  // the code to ignore this case for stores.
+  // TODO(karl): Should we not allow this?
+  // if (HasWriteBack(i) && n.reg(i).Equals(t2.reg(i))) {
+  //   return UNPREDICTABLE;
+  // }
 
   // Now apply non-double width restrictions for this instruction.
   return StrImmediate::safety(i);
 }
 
 SafetyLevel StoreRegister::safety(const Instruction i) const {
   if (PreindexingFlag(i)) {
     // Computes base address by adding two registers -- cannot predict!
     return FORBIDDEN;
   }
@@ skipping 24 matching lines @@
     // to it, so it is not safe. (NaCl constraint).
     return FORBIDDEN;
   }
 
   // Arm restrictions for this instruction.
   if (RegisterList(t.reg(i)).Add(m.reg(i)).Contains(kRegisterPc)) {
     return UNPREDICTABLE;
   }
 
   if (HasWriteBack(i) &&
-      (n.reg(i).Equals(kRegisterPc) || n.reg(i).Equals(t.reg(i)))) {
+      (n.reg(i).Equals(kRegisterPc))) {
+    // NOTE: The manual states that that it is also unpredictable
+    // when HasWriteBack(i) and Rn=Rt. However, the compilers
+    // may not check for this. For the moment, we are changing
+    // the code to ignore this case for stores.
+    // TODO(karl): Should we not allow this?
     return UNPREDICTABLE;
   }
 
   // Don't let addressing writeback alter PC (NaCl constraint).
   if (defs(i).Contains(kRegisterPc)) return FORBIDDEN_OPERANDS;
 
   return MAY_BE_SAFE;
 }
 
 SafetyLevel StoreExclusive::safety(const Instruction i) const {
@@ skipping 160 matching lines @@
   // Arm double width restrictions for this instruction.
   if (!t.IsEven(i)) {
     return UNDEFINED;
   }
 
   if (RegisterList(t2.reg(i)).Add(m.reg(i)).Contains(kRegisterPc)) {
     return UNPREDICTABLE;
   }
 
   if (HasWriteBack(i) &&
-      (n.reg(i).Equals(kRegisterPc) || n.reg(i).Equals(t.reg(i)) ||
-       n.reg(i).Equals(t2.reg(i)))) {
+      (n.reg(i).Equals(kRegisterPc))) {
+    // NOTE: The manual states that that it is also unpredictable
+    // when HasWriteBack(i) and Rn=Rt or Rn=Rt2. However, the compilers
+    // may not check for this. For the moment, we are changing
+    // the code to ignore this case for stores.
+    // TODO(karl): Should we not allow this?
     return UNPREDICTABLE;
   }
 
   // Now apply non-double width restrictions for this instruction.
   return StrRegister::safety(i);
 }
 
 Register LoadExclusive::base_address_register(const Instruction i) const {
   return Rn(i);
 }
@@ skipping 140 matching lines @@
       Add(PreindexingFlag(i) ? kRegisterLink : kRegisterNone);
 }
 
 int32_t Branch::branch_target_offset(const Instruction i) const {
   // Sign extend and shift left 2:
   int32_t offset = (int32_t)(i.Bits(23, 0) << 8) >> 6;
   return offset + 8;  // because r15 reads as 8 bytes ahead
 }
 
 }  // namespace