Define a baseline and testing patterns for ARM load_store_word_byte table.

src/trusted/validator_arm/gen/arm32_decode.cc

 /*
  * Copyright 2012 The Native Client Authors.  All rights reserved.
  * Use of this source code is governed by a BSD-style license that can
  * be found in the LICENSE file.
  */
 
 // DO NOT EDIT: GENERATED CODE
 
 
 #include "native_client/src/trusted/validator_arm/gen/arm32_decode.h"
@@ skipping 23 matching lines @@
   , DontCareInst_instance_()
   , EffectiveNoOp_instance_()
   , Forbidden_instance_()
   , LdrImmediate_instance_()
   , LdrImmediateDouble_instance_()
   , LdrRegister_instance_()
   , LdrRegisterDouble_instance_()
   , LoadCoprocessor_instance_()
   , LoadDoubleExclusive_instance_()
   , LoadExclusive_instance_()
-  , LoadImmediate_instance_()
   , LoadMultiple_instance_()
-  , LoadRegister_instance_()
   , LongMultiply_instance_()
   , MaskAddress_instance_()
   , MoveDoubleFromCoprocessor_instance_()
   , MoveFromCoprocessor_instance_()
   , MoveToStatusRegister_instance_()
   , Multiply_instance_()
   , PackSatRev_instance_()
   , Roadblock_instance_()
   , SatAddSub_instance_()
   , StoreCoprocessor_instance_()
   , StoreExclusive_instance_()
   , StoreImmediate_instance_()
-  , StoreRegister_instance_()
   , StrImmediate_instance_()
   , StrImmediateDouble_instance_()
   , StrRegister_instance_()
   , StrRegisterDouble_instance_()
   , TestIfAddressMasked_instance_()
   , Unary1RegisterBitRange_instance_()
   , Unary1RegisterImmediateOp_instance_()
   , Unary3RegisterShiftedOp_instance_()
   , Undefined_instance_()
   , Unpredictable_instance_()
@@ skipping 379 matching lines @@
 
 // Implementation of table: load_store_word_byte.
 // Specified by: See Section A5.3
 const ClassDecoder& Arm32DecoderState::decode_load_store_word_byte(
      const Instruction insn) const
 {
   UNREFERENCED_PARAMETER(insn);
   if ((insn.Bits() & 0x02000000) == 0x00000000 /* A(25:25) == 0 */ &&
       (insn.Bits() & 0x01300000) == 0x00000000 /* op1(24:20) == 0xx00 */ &&
       true)
-    return StoreImmediate_instance_;
+    return StrImmediate_instance_;
 
   if ((insn.Bits() & 0x02000000) == 0x00000000 /* A(25:25) == 0 */ &&
       (insn.Bits() & 0x01300000) == 0x00100000 /* op1(24:20) == 0xx01 */ &&
       true)
-    return LoadImmediate_instance_;
+    return LdrImmediate_instance_;
 
   if ((insn.Bits() & 0x02000000) == 0x00000000 /* A(25:25) == 0 */ &&
       (insn.Bits() & 0x01100000) == 0x01000000 /* op1(24:20) == 1xxx0 */ &&
       true)
-    return StoreImmediate_instance_;
+    return StrImmediate_instance_;
 
   if ((insn.Bits() & 0x02000000) == 0x00000000 /* A(25:25) == 0 */ &&
       (insn.Bits() & 0x01100000) == 0x01100000 /* op1(24:20) == 1xxx1 */ &&
       true)
-    return LoadImmediate_instance_;
+    return LdrImmediate_instance_;
 
   if ((insn.Bits() & 0x02000000) == 0x00000000 /* A(25:25) == 0 */ &&
       (insn.Bits() & 0x01200000) == 0x00200000 /* op1(24:20) == 0xx1x */ &&
       true)
     return Forbidden_instance_;
 
   if ((insn.Bits() & 0x02000000) == 0x02000000 /* A(25:25) == 1 */ &&
       (insn.Bits() & 0x01700000) == 0x00500000 /* op1(24:20) == 0x101 */ &&
       (insn.Bits() & 0x00000010) == 0x00000000 /* B(4:4) == 0 */)
-    return LoadRegister_instance_;
+    return LdrRegister_instance_;
 
   if ((insn.Bits() & 0x02000000) == 0x02000000 /* A(25:25) == 1 */ &&
       (insn.Bits() & 0x00700000) == 0x00100000 /* op1(24:20) == xx001 */ &&
       (insn.Bits() & 0x00000010) == 0x00000000 /* B(4:4) == 0 */)
-    return LoadRegister_instance_;
+    return LdrRegister_instance_;
 
   if ((insn.Bits() & 0x02000000) == 0x02000000 /* A(25:25) == 1 */ &&
       (insn.Bits() & 0x01300000) == 0x00000000 /* op1(24:20) == 0xx00 */ &&
       (insn.Bits() & 0x00000010) == 0x00000000 /* B(4:4) == 0 */)
-    return StoreRegister_instance_;
+    return StrRegister_instance_;
 
   if ((insn.Bits() & 0x02000000) == 0x02000000 /* A(25:25) == 1 */ &&
       (insn.Bits() & 0x01100000) == 0x01000000 /* op1(24:20) == 1xxx0 */ &&
       (insn.Bits() & 0x00000010) == 0x00000000 /* B(4:4) == 0 */)
-    return StoreRegister_instance_;
+    return StrRegister_instance_;
 
   if ((insn.Bits() & 0x02000000) == 0x02000000 /* A(25:25) == 1 */ &&
       (insn.Bits() & 0x01100000) == 0x01100000 /* op1(24:20) == 1xxx1 */ &&
       (insn.Bits() & 0x00000010) == 0x00000000 /* B(4:4) == 0 */)
-    return LoadRegister_instance_;
+    return LdrRegister_instance_;
 
   if ((insn.Bits() & 0x02000000) == 0x02000000 /* A(25:25) == 1 */ &&
       (insn.Bits() & 0x01200000) == 0x00200000 /* op1(24:20) == 0xx1x */ &&
       (insn.Bits() & 0x00000010) == 0x00000000 /* B(4:4) == 0 */)
     return Forbidden_instance_;
 
   // Catch any attempt to fall though ...
   fprintf(stderr, "TABLE IS INCOMPLETE: load_store_word_byte could not parse %08X",
           insn.Bits());
   return Forbidden_instance_;
@@ skipping 1181 matching lines @@
   fprintf(stderr, "TABLE IS INCOMPLETE: unconditional could not parse %08X",
           insn.Bits());
   return Forbidden_instance_;
 }
 
 const ClassDecoder& Arm32DecoderState::decode(const Instruction insn) const {
   return decode_ARMv7(insn);
 }
 
 }  // namespace nacl_arm_dec