Clean up testing of instructions. Allow testing to quit if test pattern tests

src/trusted/validator_arm/inst_classes_testers.cc

Index: src/trusted/validator_arm/inst_classes_testers.cc
===================================================================
--- src/trusted/validator_arm/inst_classes_testers.cc	(revision 8517)
+++ src/trusted/validator_arm/inst_classes_testers.cc	(working copy)
@@ -25,7 +25,7 @@
     const NamedClassDecoder& decoder)
     : Arm32DecoderTester(decoder) {}
 
-void Unary1RegisterImmediateOpTester::
+bool Unary1RegisterImmediateOpTester::
 ApplySanityChecks(Instruction inst,
                   const NamedClassDecoder& decoder) {
   nacl_arm_dec::Unary1RegisterImmediateOp expected_decoder;
@@ -34,12 +34,12 @@
   EXPECT_EQ(expected_decoder.cond.value(inst), inst.bits(31, 28));
 
   // Didn't parse undefined conditional.
-  if (expected_decoder.cond.undefined(inst) &&
-      (&ExpectedDecoder() != &decoder))
-    return;
+  if (expected_decoder.cond.undefined(inst)) {
+    NC_EXPECT_NE_PRECOND(&ExpectedDecoder(), &decoder);
+  }
 
   // Check if expected class name found.
-  Arm32DecoderTester::ApplySanityChecks(inst, decoder);
+  NC_PRECOND(Arm32DecoderTester::ApplySanityChecks(inst, decoder));
 
   // Check Registers and flags used in DataProc.
   EXPECT_EQ(expected_decoder.d.number(inst), inst.bits(15, 12));
@@ -60,6 +60,8 @@
   // Other NaCl constraints about this instruction.
   EXPECT_NE(expected_decoder.d.number(inst), (uint32_t) 15)
       << "Expected FORBIDDEN_OPERANDS for " << InstContents();
+
+  return true;
 }
 
 // Unary1RegisterImmediateOpTesterRegsNotPc
@@ -68,22 +70,25 @@
     const NamedClassDecoder& decoder)
     : Unary1RegisterImmediateOpTester(decoder) {}
 
-void Unary1RegisterImmediateOpTesterRegsNotPc::
+bool Unary1RegisterImmediateOpTesterRegsNotPc::
 ApplySanityChecks(Instruction inst,
                   const NamedClassDecoder& decoder) {
   nacl_arm_dec::Unary1RegisterImmediateOp expected_decoder;
-  Unary1RegisterImmediateOpTester::ApplySanityChecks(inst, decoder);
 
+  NC_PRECOND(Unary1RegisterImmediateOpTester::ApplySanityChecks(inst, decoder));
+
   // Other ARM constraints about this instruction.
   EXPECT_NE(expected_decoder.d.number(inst), (uint32_t) 15)
       << "Expected Unpredictable for " << InstContents();
+
+  return true;
 }
 
 Binary2RegisterImmediateOpTester::Binary2RegisterImmediateOpTester(
     const NamedClassDecoder& decoder)
     : Arm32DecoderTester(decoder), apply_rd_is_pc_check_(true) {}
 
-void Binary2RegisterImmediateOpTester::
+bool Binary2RegisterImmediateOpTester::
 ApplySanityChecks(Instruction inst,
                   const NamedClassDecoder& decoder) {
   nacl_arm_dec::Binary2RegisterImmediateOp expected_decoder;
@@ -92,12 +97,12 @@
   EXPECT_EQ(expected_decoder.cond.value(inst), inst.bits(31, 28));
 
   // Didn't parse undefined conditional.
-  if (expected_decoder.cond.undefined(inst) &&
-      (&ExpectedDecoder() != &decoder))
-    return;
+  if (expected_decoder.cond.undefined(inst)) {
+    NC_EXPECT_NE_PRECOND(&ExpectedDecoder(), &decoder);
+  }
 
   // Check if expected class name found.
-  Arm32DecoderTester::ApplySanityChecks(inst, decoder);
+  NC_PRECOND(Arm32DecoderTester::ApplySanityChecks(inst, decoder));
 
   // Check Registers and flags used in DataProc.
   EXPECT_EQ(expected_decoder.n.number(inst), inst.bits(19, 16));
@@ -117,6 +122,8 @@
     EXPECT_NE(expected_decoder.d.number(inst), (uint32_t) 15)
         << "Expected FORBIDDEN_OPERANDS for " << InstContents();
   }
+
+  return true;
 }
 
 // Binary2RegisterImmediateOpTesterNotRdIsPcAndS
@@ -125,17 +132,18 @@
     const NamedClassDecoder& decoder)
     : Binary2RegisterImmediateOpTester(decoder) {}
 
-void Binary2RegisterImmediateOpTesterNotRdIsPcAndS::
+bool Binary2RegisterImmediateOpTesterNotRdIsPcAndS::
 ApplySanityChecks(Instruction inst,
                   const NamedClassDecoder& decoder) {
   nacl_arm_dec::Binary2RegisterImmediateOp expected_decoder;
 
   // Check that we don't parse when Rd=15 and S=1.
   if ((expected_decoder.d.reg(inst) == kRegisterPc) &&
-      expected_decoder.flags.is_updated(inst) &&
-      (&ExpectedDecoder() != &decoder))
-    return;
-  Binary2RegisterImmediateOpTester::ApplySanityChecks(inst, decoder);
+      expected_decoder.flags.is_updated(inst)) {
+    NC_EXPECT_NE_PRECOND(&ExpectedDecoder(), &decoder);
+  }
+
+  return Binary2RegisterImmediateOpTester::ApplySanityChecks(inst, decoder);
 }
 
 // Binary2RegisterImmediateOpTesterRdCanBePcAndNotRdIsPcAndS
@@ -151,7 +159,7 @@
     const NamedClassDecoder& decoder)
     : Arm32DecoderTester(decoder) {}
 
-void BinaryRegisterImmediateTestTester::
+bool BinaryRegisterImmediateTestTester::
 ApplySanityChecks(Instruction inst,
                   const NamedClassDecoder& decoder) {
   nacl_arm_dec::BinaryRegisterImmediateTest expected_decoder;
@@ -160,12 +168,12 @@
   EXPECT_EQ(expected_decoder.cond.value(inst), inst.bits(31, 28));
 
   // Didn't parse undefined conditional.
-  if (expected_decoder.cond.undefined(inst) &&
-      (&ExpectedDecoder() != &decoder))
-    return;
+  if (expected_decoder.cond.undefined(inst)) {
+    NC_EXPECT_NE_PRECOND(&ExpectedDecoder(), &decoder);
+  }
 
   // Check if expected class name found.
-  Arm32DecoderTester::ApplySanityChecks(inst, decoder);
+  NC_PRECOND(Arm32DecoderTester::ApplySanityChecks(inst, decoder));
 
   // Check Registers and flags used in DataProc.
   EXPECT_EQ(expected_decoder.n.number(inst), inst.bits(19, 16));
@@ -178,6 +186,8 @@
 
   // Check that immediate value is computed correctly.
   EXPECT_EQ(expected_decoder.imm.value(inst), inst.bits(11, 0));
+
+  return true;
 }
 
 // Unary2RegisterOpTester
@@ -185,7 +195,7 @@
     const NamedClassDecoder& decoder)
     : Arm32DecoderTester(decoder) {}
 
-void Unary2RegisterOpTester::
+bool Unary2RegisterOpTester::
 ApplySanityChecks(Instruction inst,
                   const NamedClassDecoder& decoder) {
   nacl_arm_dec::Unary2RegisterOp expected_decoder;
@@ -194,12 +204,12 @@
   EXPECT_EQ(expected_decoder.cond.value(inst), inst.bits(31, 28));
 
   // Didn't parse undefined conditional.
-  if (expected_decoder.cond.undefined(inst) &&
-      (&ExpectedDecoder() != &decoder))
-    return;
+  if (expected_decoder.cond.undefined(inst)) {
+    NC_EXPECT_NE_PRECOND(&ExpectedDecoder(), &decoder);
+  }
 
   // Check if expected class name found.
-  Arm32DecoderTester::ApplySanityChecks(inst, decoder);
+  NC_PRECOND(!Arm32DecoderTester::ApplySanityChecks(inst, decoder));
 
   // Check Registers and flags used in DataProc.
   EXPECT_EQ(expected_decoder.d.number(inst), inst.bits(15, 12));
@@ -214,6 +224,8 @@
   // Other NaCl constraints about this instruction.
   EXPECT_NE(expected_decoder.d.number(inst), (uint32_t) 15)
       << "Expected FORBIDDEN_OPERANDS for " << InstContents();
+
+  return true;
 }
 
 // Unary2RegisterOpTesterNotRdIsPcAndS
@@ -222,17 +234,18 @@
     : Unary2RegisterOpTester(decoder) {}
 
 
-void Unary2RegisterOpTesterNotRdIsPcAndS::
+bool Unary2RegisterOpTesterNotRdIsPcAndS::
 ApplySanityChecks(Instruction inst,
                   const NamedClassDecoder& decoder) {
   nacl_arm_dec::Unary2RegisterOp expected_decoder;
 
   // Check that we don't parse when Rd=15 and S=1.
   if ((expected_decoder.d.reg(inst) == kRegisterPc) &&
-      expected_decoder.flags.is_updated(inst) &&
-      (&ExpectedDecoder() != &decoder))
-    return;
-  Unary2RegisterOpTester::ApplySanityChecks(inst, decoder);
+      expected_decoder.flags.is_updated(inst)) {
+    NC_EXPECT_NE_PRECOND(&ExpectedDecoder(), &decoder);
+  }
+
+  return Unary2RegisterOpTester::ApplySanityChecks(inst, decoder);
 }
 
 // Binary3RegisterOpTester
@@ -240,7 +253,7 @@
     const NamedClassDecoder& decoder)
     : Arm32DecoderTester(decoder) {}
 
-void Binary3RegisterOpTester::
+bool Binary3RegisterOpTester::
 ApplySanityChecks(Instruction inst,
                   const NamedClassDecoder& decoder) {
   nacl_arm_dec::Binary3RegisterOp expected_decoder;
@@ -249,12 +262,12 @@
   EXPECT_EQ(expected_decoder.cond.value(inst), inst.bits(31, 28));
 
   // Didn't parse undefined conditional.
-  if (expected_decoder.cond.undefined(inst) &&
-      (&ExpectedDecoder() != &decoder))
-    return;
+  if (expected_decoder.cond.undefined(inst)) {
+    NC_EXPECT_NE_PRECOND(&ExpectedDecoder(), &decoder);
+  }
 
   // Check if expected class name found.
-  Arm32DecoderTester::ApplySanityChecks(inst, decoder);
+  NC_PRECOND(Arm32DecoderTester::ApplySanityChecks(inst, decoder));
 
   // Check Registers and flags used in DataProc.
   EXPECT_EQ(expected_decoder.d.number(inst), inst.bits(15, 12));
@@ -270,6 +283,8 @@
   // Other NaCl constraints about this instruction.
   EXPECT_NE(expected_decoder.d.number(inst), (uint32_t) 15)
       << "Expected FORBIDDEN_OPERANDS for " << InstContents();
+
+  return true;
 }
 
 // Binary3RegisterOpTesterRegsNotPc
@@ -277,12 +292,13 @@
     const NamedClassDecoder& decoder)
     : Binary3RegisterOpTester(decoder) {}
 
-void Binary3RegisterOpTesterRegsNotPc::
+bool Binary3RegisterOpTesterRegsNotPc::
 ApplySanityChecks(Instruction inst,
                   const NamedClassDecoder& decoder) {
   nacl_arm_dec::Binary3RegisterOp expected_decoder;
-  Binary3RegisterOpTester::ApplySanityChecks(inst, decoder);
 
+  NC_PRECOND(Binary3RegisterOpTester::ApplySanityChecks(inst, decoder));
+
   // Other ARM constraints about this instruction.
   EXPECT_NE(expected_decoder.d.number(inst), (uint32_t) 15)
       << "Expected Unpredictable for " << InstContents();
@@ -290,6 +306,8 @@
       << "Expected Unpredictable for " << InstContents();
   EXPECT_NE(expected_decoder.n.number(inst), (uint32_t) 15)
       << "Expected Unpredictable for " << InstContents();
+
+  return true;
 }
 
 // Unary2RegisterImmedShiftedOpTester
@@ -297,7 +315,7 @@
     const NamedClassDecoder& decoder)
     : Arm32DecoderTester(decoder) {}
 
-void Unary2RegisterImmedShiftedOpTester::
+bool Unary2RegisterImmedShiftedOpTester::
 ApplySanityChecks(Instruction inst,
                   const NamedClassDecoder& decoder) {
   nacl_arm_dec::Unary2RegisterImmedShiftedOp expected_decoder;
@@ -306,12 +324,12 @@
   EXPECT_EQ(expected_decoder.cond.value(inst), inst.bits(31, 28));
 
   // Didn't parse undefined conditional.
-  if (expected_decoder.cond.undefined(inst) &&
-      (&ExpectedDecoder() != &decoder))
-    return;
+  if (expected_decoder.cond.undefined(inst)) {
+    NC_EXPECT_NE_PRECOND(&ExpectedDecoder(), &decoder);
+  }
 
   // Check if expected class name found.
-  Arm32DecoderTester::ApplySanityChecks(inst, decoder);
+  NC_PRECOND(Arm32DecoderTester::ApplySanityChecks(inst, decoder));
 
   // Check Registers and flags used in DataProc.
   EXPECT_EQ(expected_decoder.d.number(inst), inst.bits(15, 12));
@@ -330,6 +348,8 @@
   // Other NaCl constraints about this instruction.
   EXPECT_NE(expected_decoder.d.number(inst), (uint32_t) 15)
       << "Expected FORBIDDEN_OPERANDS for " << InstContents();
+
+  return true;
 }
 
 // Unary2RegisterImmedShiftedOpTesterImm5NotZero
@@ -338,16 +358,17 @@
     const NamedClassDecoder& decoder)
     : Unary2RegisterImmedShiftedOpTester(decoder) {}
 
-void Unary2RegisterImmedShiftedOpTesterImm5NotZero::
+bool Unary2RegisterImmedShiftedOpTesterImm5NotZero::
 ApplySanityChecks(Instruction inst,
                   const NamedClassDecoder& decoder) {
   nacl_arm_dec::Unary2RegisterImmedShiftedOp expected_decoder;
 
   // Check that we don't parse when imm5=0.
-  if ((0 == expected_decoder.imm.value(inst)) &&
-      (&ExpectedDecoder() != &decoder))
-    return;
-  Unary2RegisterImmedShiftedOpTester::ApplySanityChecks(inst, decoder);
+  if (0 == expected_decoder.imm.value(inst)) {
+    NC_EXPECT_NE_PRECOND(&ExpectedDecoder(), &decoder);
+  }
+
+  return Unary2RegisterImmedShiftedOpTester::ApplySanityChecks(inst, decoder);
 }
 
 // Unary2RegisterImmedShiftedOpTesterNotRdIsPcAndS
@@ -356,17 +377,18 @@
     const NamedClassDecoder& decoder)
     : Unary2RegisterImmedShiftedOpTester(decoder) {}
 
-void Unary2RegisterImmedShiftedOpTesterNotRdIsPcAndS::
+bool Unary2RegisterImmedShiftedOpTesterNotRdIsPcAndS::
 ApplySanityChecks(Instruction inst,
                   const NamedClassDecoder& decoder) {
   nacl_arm_dec::Unary2RegisterImmedShiftedOp expected_decoder;
 
   // Check that we don't parse when Rd=15 and S=1.
   if ((expected_decoder.d.reg(inst) == kRegisterPc) &&
-      expected_decoder.flags.is_updated(inst) &&
-      (&ExpectedDecoder() != &decoder))
-    return;
-  Unary2RegisterImmedShiftedOpTester::ApplySanityChecks(inst, decoder);
+      expected_decoder.flags.is_updated(inst)) {
+    NC_EXPECT_NE_PRECOND(&ExpectedDecoder(), &decoder);
+  }
+
+  return Unary2RegisterImmedShiftedOpTester::ApplySanityChecks(inst, decoder);
 }
 
 // Unary3RegisterShiftedOpTester
@@ -374,7 +396,7 @@
     const NamedClassDecoder& decoder)
     : Arm32DecoderTester(decoder) {}
 
-void Unary3RegisterShiftedOpTester::
+bool Unary3RegisterShiftedOpTester::
 ApplySanityChecks(Instruction inst,
                   const NamedClassDecoder& decoder) {
   nacl_arm_dec::Unary3RegisterShiftedOp expected_decoder;
@@ -383,12 +405,12 @@
   EXPECT_EQ(expected_decoder.cond.value(inst), inst.bits(31, 28));
 
   // Didn't parse undefined conditional.
-  if (expected_decoder.cond.undefined(inst) &&
-      (&ExpectedDecoder() != &decoder))
-    return;
+  if (expected_decoder.cond.undefined(inst)) {
+    NC_EXPECT_NE_PRECOND(&ExpectedDecoder(), &decoder);
+  }
 
   // Check if expected class name found.
-  Arm32DecoderTester::ApplySanityChecks(inst, decoder);
+  NC_PRECOND(Arm32DecoderTester::ApplySanityChecks(inst, decoder));
 
   // Check Registers and flags used in DataProc.
   EXPECT_EQ(expected_decoder.d.number(inst), inst.bits(15, 12));
@@ -407,6 +429,8 @@
   // Other NaCl constraints about this instruction.
   EXPECT_NE(expected_decoder.d.number(inst), (uint32_t) 15)
       << "Expected FORBIDDEN_OPERANDS for " << InstContents();
+
+  return true;
 }
 
 // Unary3RegisterShiftedOpTesterRegsNotPc
@@ -414,12 +438,12 @@
     const NamedClassDecoder& decoder)
     : Unary3RegisterShiftedOpTester(decoder) {}
 
-void Unary3RegisterShiftedOpTesterRegsNotPc::
+bool Unary3RegisterShiftedOpTesterRegsNotPc::
 ApplySanityChecks(Instruction inst,
                   const NamedClassDecoder& decoder) {
   nacl_arm_dec::Unary3RegisterShiftedOp expected_decoder;
 
-  Unary3RegisterShiftedOpTester::ApplySanityChecks(inst, decoder);
+  NC_PRECOND(Unary3RegisterShiftedOpTester::ApplySanityChecks(inst, decoder));
 
   // Other ARM constraints about this instruction.
   EXPECT_NE(expected_decoder.d.number(inst), (uint32_t) 15)
@@ -428,6 +452,8 @@
       << "Expected Unpredictable for " << InstContents();
   EXPECT_NE(expected_decoder.m.number(inst), (uint32_t) 15)
       << "Expected Unpredictable for " << InstContents();
+
+  return true;
 }
 
 // Binary3RegisterImmedShiftedOpTester
@@ -435,7 +461,7 @@
     const NamedClassDecoder& decoder)
     : Arm32DecoderTester(decoder) {}
 
-void Binary3RegisterImmedShiftedOpTester::
+bool Binary3RegisterImmedShiftedOpTester::
 ApplySanityChecks(Instruction inst,
                   const NamedClassDecoder& decoder) {
   nacl_arm_dec::Binary3RegisterImmedShiftedOp expected_decoder;
@@ -444,12 +470,12 @@
   EXPECT_EQ(expected_decoder.cond.value(inst), inst.bits(31, 28));
 
   // Didn't parse undefined conditional.
-  if (expected_decoder.cond.undefined(inst) &&
-      (&ExpectedDecoder() != &decoder))
-    return;
+  if (expected_decoder.cond.undefined(inst)) {
+    NC_EXPECT_NE_PRECOND(&ExpectedDecoder(), &decoder);
+  }
 
   // Check if expected class name found.
-  Arm32DecoderTester::ApplySanityChecks(inst, decoder);
+  NC_PRECOND(Arm32DecoderTester::ApplySanityChecks(inst, decoder));
 
   // Check Registers and flags used in DataProc.
   EXPECT_EQ(expected_decoder.n.number(inst), inst.bits(19, 16));
@@ -469,6 +495,8 @@
   // Other NaCl constraints about this instruction.
   EXPECT_NE(expected_decoder.d.number(inst), (uint32_t) 15)
       << "Expected FORBIDDEN_OPERANDS for " << InstContents();
+
+  return true;
 }
 
 // Binary3RegisterImmedShiftedOpTesterNotRdIsPcAndS
@@ -477,17 +505,18 @@
     const NamedClassDecoder& decoder)
     : Binary3RegisterImmedShiftedOpTester(decoder) {}
 
-void Binary3RegisterImmedShiftedOpTesterNotRdIsPcAndS::
+bool Binary3RegisterImmedShiftedOpTesterNotRdIsPcAndS::
 ApplySanityChecks(Instruction inst,
                   const NamedClassDecoder& decoder) {
   nacl_arm_dec::Binary3RegisterImmedShiftedOp expected_decoder;
 
   // Check that we don't parse when Rd=15 and S=1.
   if ((expected_decoder.d.reg(inst) == kRegisterPc) &&
-      expected_decoder.flags.is_updated(inst) &&
-      (&ExpectedDecoder() != &decoder))
-    return;
-  Binary3RegisterImmedShiftedOpTester::ApplySanityChecks(inst, decoder);
+      expected_decoder.flags.is_updated(inst)) {
+    NC_EXPECT_NE_PRECOND(&ExpectedDecoder(), &decoder);
+  }
+
+  return Binary3RegisterImmedShiftedOpTester::ApplySanityChecks(inst, decoder);
 }
 
 // Binary3RegisterImmedShiftedOpTesterNotRdIsPcAndSOrRnIsSp
@@ -496,16 +525,17 @@
     const NamedClassDecoder& decoder)
     : Binary3RegisterImmedShiftedOpTesterNotRdIsPcAndS(decoder) {}
 
-void Binary3RegisterImmedShiftedOpTesterNotRdIsPcAndSOrRnIsSp::
+bool Binary3RegisterImmedShiftedOpTesterNotRdIsPcAndSOrRnIsSp::
 ApplySanityChecks(Instruction inst,
                   const NamedClassDecoder& decoder) {
   nacl_arm_dec::Binary3RegisterImmedShiftedOp expected_decoder;
 
   // Check that we don't parse when Rn=13
-  if ((expected_decoder.n.reg(inst) == kRegisterStack) &&
-      (&ExpectedDecoder() != &decoder))
-    return;
-  Binary3RegisterImmedShiftedOpTesterNotRdIsPcAndS::
+  if (expected_decoder.n.reg(inst) == kRegisterStack) {
+    NC_EXPECT_NE_PRECOND(&ExpectedDecoder(), &decoder);
+  }
+
+  return Binary3RegisterImmedShiftedOpTesterNotRdIsPcAndS::
       ApplySanityChecks(inst, decoder);
 }
 
@@ -514,7 +544,7 @@
     const NamedClassDecoder& decoder)
       : Arm32DecoderTester(decoder) {}
 
-void Binary4RegisterShiftedOpTester::
+bool Binary4RegisterShiftedOpTester::
 ApplySanityChecks(Instruction inst,
                   const NamedClassDecoder& decoder) {
   nacl_arm_dec::Binary4RegisterShiftedOp expected_decoder;
@@ -523,12 +553,12 @@
   EXPECT_EQ(expected_decoder.cond.value(inst), inst.bits(31, 28));
 
   // Didn't parse undefined conditional.
-  if (expected_decoder.cond.undefined(inst) &&
-      (&ExpectedDecoder() != &decoder))
-    return;
+  if (expected_decoder.cond.undefined(inst)) {
+    NC_EXPECT_NE_PRECOND(&ExpectedDecoder(), &decoder);
+  }
 
   // Check if expected class name found.
-  Arm32DecoderTester::ApplySanityChecks(inst, decoder);
+  NC_PRECOND(Arm32DecoderTester::ApplySanityChecks(inst, decoder));
 
   // Check Registers and flags used in DataProc.
   EXPECT_EQ(expected_decoder.n.number(inst), inst.bits(19, 16));
@@ -545,6 +575,8 @@
   // Other NaCl constraints about this instruction.
   EXPECT_NE(expected_decoder.d.number(inst), (uint32_t) 15)
       << "Expected FORBIDDEN_OPERANDS for " << InstContents();
+
+  return true;
 }
 
 // Binary4RegisterShiftedOpTesterRegsNotPc
@@ -553,12 +585,13 @@
     const NamedClassDecoder& decoder)
       : Binary4RegisterShiftedOpTester(decoder) {}
 
-void Binary4RegisterShiftedOpTesterRegsNotPc::
+bool Binary4RegisterShiftedOpTesterRegsNotPc::
 ApplySanityChecks(Instruction inst,
                   const NamedClassDecoder& decoder) {
   nacl_arm_dec::Binary4RegisterShiftedOp expected_decoder;
-  Binary4RegisterShiftedOpTester::ApplySanityChecks(inst, decoder);
 
+  NC_PRECOND(Binary4RegisterShiftedOpTester::ApplySanityChecks(inst, decoder));
+
   // Other ARM constraints about this instruction.
   EXPECT_NE(expected_decoder.n.reg(inst), kRegisterPc)
       << "Expected Unpredictable for " << InstContents();
@@ -568,6 +601,8 @@
       << "Expected Unpredictable for " << InstContents();
   EXPECT_NE(expected_decoder.m.reg(inst), kRegisterPc)
       << "Expected Unpredictable for " << InstContents();
+
+  return true;
 }
 
 // Binary2RegisterImmedShiftedTestTester
@@ -575,7 +610,7 @@
     const NamedClassDecoder& decoder)
     : Arm32DecoderTester(decoder) {}
 
-void Binary2RegisterImmedShiftedTestTester::
+bool Binary2RegisterImmedShiftedTestTester::
 ApplySanityChecks(Instruction inst,
                   const NamedClassDecoder& decoder) {
   nacl_arm_dec::Binary2RegisterImmedShiftedTest expected_decoder;
@@ -584,12 +619,12 @@
   EXPECT_EQ(expected_decoder.cond.value(inst), inst.bits(31, 28));
 
   // Didn't parse undefined conditional.
-  if (expected_decoder.cond.undefined(inst) &&
-      (&ExpectedDecoder() != &decoder))
-    return;
+  if (expected_decoder.cond.undefined(inst)) {
+    NC_EXPECT_NE_PRECOND(&ExpectedDecoder(), &decoder);
+  }
 
   // Check if expected class name found.
-  Arm32DecoderTester::ApplySanityChecks(inst, decoder);
+  NC_PRECOND(Arm32DecoderTester::ApplySanityChecks(inst, decoder));
 
   // Check Registers and flags used in DataProc.
   EXPECT_EQ(expected_decoder.n.number(inst), inst.bits(19, 16));
@@ -604,6 +639,8 @@
   // Check that immediate value is computed correctly.
   EXPECT_EQ(expected_decoder.imm.value(inst), inst.bits(11, 7));
   EXPECT_EQ(expected_decoder.shift_type.value(inst), inst.bits(6, 5));
+
+  return true;
 }
 
 // Binary3RegisterShiftedTestTester
@@ -611,7 +648,7 @@
     const NamedClassDecoder& decoder)
     : Arm32DecoderTester(decoder) {}
 
-void Binary3RegisterShiftedTestTester::
+bool Binary3RegisterShiftedTestTester::
 ApplySanityChecks(Instruction inst,
                   const NamedClassDecoder& decoder) {
   nacl_arm_dec::Binary3RegisterShiftedTest expected_decoder;
@@ -620,12 +657,12 @@
   EXPECT_EQ(expected_decoder.cond.value(inst), inst.bits(31, 28));
 
   // Didn't parse undefined conditional.
-  if (expected_decoder.cond.undefined(inst) &&
-      (&ExpectedDecoder() != &decoder))
-    return;
+  if (expected_decoder.cond.undefined(inst)) {
+    NC_EXPECT_NE_PRECOND(&ExpectedDecoder(), &decoder);
+  }
 
   // Check if expected class name found.
-  Arm32DecoderTester::ApplySanityChecks(inst, decoder);
+  NC_PRECOND(Arm32DecoderTester::ApplySanityChecks(inst, decoder));
 
   // Check Registers and flags used in DataProc.
   EXPECT_EQ(expected_decoder.n.number(inst), inst.bits(19, 16));
@@ -638,6 +675,8 @@
     EXPECT_EQ(expected_decoder.flags.reg_if_updated(inst), kRegisterNone);
   }
   EXPECT_EQ(expected_decoder.shift_type.value(inst), inst.bits(6, 5));
+
+  return true;
 }
 
 // Binary3RegisterShiftedTestTesterRegsNotPc
@@ -646,12 +685,14 @@
     const NamedClassDecoder& decoder)
     : Binary3RegisterShiftedTestTester(decoder) {}
 
-void Binary3RegisterShiftedTestTesterRegsNotPc::
+bool Binary3RegisterShiftedTestTesterRegsNotPc::
 ApplySanityChecks(Instruction inst,
                   const NamedClassDecoder& decoder) {
   nacl_arm_dec::Binary3RegisterShiftedTest expected_decoder;
-  Binary3RegisterShiftedTestTester::ApplySanityChecks(inst, decoder);
 
+  NC_PRECOND(Binary3RegisterShiftedTestTester::ApplySanityChecks(
+      inst, decoder));
+
   // Other ARM constraints about this instruction.
   EXPECT_NE(expected_decoder.n.number(inst), (uint32_t) 15)
       << "Expected Unpredictable for " << InstContents();
@@ -659,6 +700,8 @@
       << "Expected Unpredictable for " << InstContents();
   EXPECT_NE(expected_decoder.m.number(inst), (uint32_t) 15)
       << "Expected Unpredictable for " << InstContents();
+
+  return true;
 }
 
 }  // namespace