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| 1 /* | 1 /* |
| 2 * Copyright (c) 2012 The Native Client Authors. All rights reserved. | 2 * Copyright (c) 2012 The Native Client Authors. All rights reserved. |
| 3 * Use of this source code is governed by a BSD-style license that can be | 3 * Use of this source code is governed by a BSD-style license that can be |
| 4 * found in the LICENSE file. | 4 * found in the LICENSE file. |
| 5 */ | 5 */ |
| 6 | 6 |
| 7 #include "native_client/src/trusted/validator_arm/baseline_classes.h" | 7 #include "native_client/src/trusted/validator_arm/baseline_classes.h" |
| 8 | 8 |
| 9 #include <assert.h> | 9 #include <assert.h> |
| 10 #include <string.h> | 10 #include <string.h> |
| (...skipping 113 matching lines...) Expand 10 before | Expand all | Expand 10 after Loading... |
| 124 SafetyLevel Binary3RegisterImmedShiftedOp::safety(const Instruction i) const { | 124 SafetyLevel Binary3RegisterImmedShiftedOp::safety(const Instruction i) const { |
| 125 // NaCl Constraint. | 125 // NaCl Constraint. |
| 126 if (d.reg(i) == kRegisterPc) return FORBIDDEN_OPERANDS; | 126 if (d.reg(i) == kRegisterPc) return FORBIDDEN_OPERANDS; |
| 127 return MAY_BE_SAFE; | 127 return MAY_BE_SAFE; |
| 128 } | 128 } |
| 129 | 129 |
| 130 RegisterList Binary3RegisterImmedShiftedOp::defs(const Instruction i) const { | 130 RegisterList Binary3RegisterImmedShiftedOp::defs(const Instruction i) const { |
| 131 return d.reg(i) + flags.reg_if_updated(i); | 131 return d.reg(i) + flags.reg_if_updated(i); |
| 132 } | 132 } |
| 133 | 133 |
| 134 // Binary3RegisterImmedShiftedOpRnNotSp |
| 135 SafetyLevel Binary3RegisterImmedShiftedOpRnNotSp:: |
| 136 safety(const Instruction i) const { |
| 137 if (n.reg(i) == kRegisterStack) return DEPRECATED; |
| 138 return Binary3RegisterImmedShiftedOp::safety(i); |
| 139 } |
| 140 |
| 134 // Binary4RegisterShiftedOp | 141 // Binary4RegisterShiftedOp |
| 135 SafetyLevel Binary4RegisterShiftedOp::safety(Instruction i) const { | 142 SafetyLevel Binary4RegisterShiftedOp::safety(Instruction i) const { |
| 136 // Unsafe if any register contains PC (ARM restriction). | 143 // Unsafe if any register contains PC (ARM restriction). |
| 137 if ((d.reg(i) + n.reg(i) + s.reg(i) + m.reg(i))[kRegisterPc]) | 144 if ((d.reg(i) + n.reg(i) + s.reg(i) + m.reg(i))[kRegisterPc]) |
| 138 return UNPREDICTABLE; | 145 return UNPREDICTABLE; |
| 139 | 146 |
| 140 // Note: We would restrict out PC as well for Rd in NaCl, but no need | 147 // Note: We would restrict out PC as well for Rd in NaCl, but no need |
| 141 // since the ARM restriction doesn't allow it anyway. | 148 // since the ARM restriction doesn't allow it anyway. |
| 142 return MAY_BE_SAFE; | 149 return MAY_BE_SAFE; |
| 143 } | 150 } |
| (...skipping 17 matching lines...) Expand all Loading... |
| 161 // Unsafe if any register contains PC (ARM restriction). | 168 // Unsafe if any register contains PC (ARM restriction). |
| 162 if ((n.reg(i) + s.reg(i) + m.reg(i))[kRegisterPc]) return UNPREDICTABLE; | 169 if ((n.reg(i) + s.reg(i) + m.reg(i))[kRegisterPc]) return UNPREDICTABLE; |
| 163 return MAY_BE_SAFE; | 170 return MAY_BE_SAFE; |
| 164 } | 171 } |
| 165 | 172 |
| 166 RegisterList Binary3RegisterShiftedTest::defs(const Instruction i) const { | 173 RegisterList Binary3RegisterShiftedTest::defs(const Instruction i) const { |
| 167 return flags.reg_if_updated(i); | 174 return flags.reg_if_updated(i); |
| 168 } | 175 } |
| 169 | 176 |
| 170 } // namespace | 177 } // namespace |
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