Clean up testing of instructions. Allow testing to quit if test pattern tests

src/trusted/validator_arm/armv7.table

 # ARMv7 Instruction Encodings
 #
 # This table is derived from the "ARM Architecture Reference Manual, ARMv7-A
 # and ARMv7-R edition" and is used here with the permission of ARM Limited.
 # Reproduction for purposes other than the development and distribution of
 # Native Client may require the explicit permission of ARM Limited.
 
 # This file defines the Native Client "instruction classes" assigned to every
 # possible ARMv7 instruction encoding.  It is organized into a series of tables,
 # and directly parallels the ARM Architecture Reference Manual cited above.
@@ skipping 61 matching lines @@
 # appropriate tester. We want to add class hierarchy information for
 # classes that want their tester to be defined on a superclass.
 # By providing this information, the generator can pick out
 # the corresponding baseline class tester to use, and does
 # not need to define separate testers for derived classes of
 # the baseline class tester.
 # #############################################################
 
 class MaskedBinary2RegisterImmediateOp : Binary2RegisterImmediateOp
 class MaskedBinaryRegisterImmediateTest : BinaryRegisterImmediateTest
+class Binary3RegisterImmedShiftedOpRnNotSp : Binary3RegisterImmedShiftedOp
 
 ##############################################################
 # The following define decoder tables.
 ##############################################################
 
 +-- ARMv7 (See Section A5.1)
 | cond(31:28) op1(27:25) op(4)
 | ~1111       00x        -     ->dp_misc
 | "           010        -     ->load_store_word_byte
 | "           011        0     ->load_store_word_byte
@@ skipping 28 matching lines @@
 +-- dp_reg (See Section A5.2.1)
 | op1(24:20) op2(11:7) op3(6:5)
 | 0000x      -         -        = Binary3RegisterImmedShiftedOp
                                      And_Rule_7_A1_P36
                                      cccc0000000unnnnddddiiiiitt0mmmm
                                      NotRdIsPcAndS
 | 0001x      -         -        = Binary3RegisterImmedShiftedOp
                                      Eor_Rule_45_A1_P96
                                      cccc0000001unnnnddddiiiiitt0mmmm
                                      NotRdIsPcAndS
-| 0010x      -         -        = Binary3RegisterImmedShiftedOp
+| 0010x      -         -        = Binary3RegisterImmedShiftedOpRnNotSp
                                      SubRule_213_A1_P422
                                      cccc0000010unnnnddddiiiiitt0mmmm
                                      NotRdIsPcAndSOrRnIsSp
 | 0011x      -         -        = Binary3RegisterImmedShiftedOp
                                      Rsb_Rule_143_P286
                                      cccc0000011unnnnddddiiiiitt0mmmm
                                      NotRdIsPcAndS
-| 0100x      -         -        = Binary3RegisterImmedShiftedOp
+| 0100x      -         -        = Binary3RegisterImmedShiftedOpRnNotSp
                                      Add_Rule_6_A1_P24
                                      cccc0000100unnnnddddiiiiitt0mmmm
                                      NotRdIsPcAndSOrRnIsSp
 | 0101x      -         -        = Binary3RegisterImmedShiftedOp
                                      Adc_Rule_2_A1_P16
                                      cccc0000101unnnnddddiiiiitt0mmmm
                                      NotRdIsPcAndS
 | 0110x      -         -        = Binary3RegisterImmedShiftedOp
                                      Sbc_Rule_152_A1_P304
                                      cccc0000110unnnnddddiiiiitt0mmmm
@@ skipping 119 matching lines @@
 | 10011      -        =Test      # TEQ(immediate)
 | 10101      -        =Test      # CMP(immediate)
 | 10111      -        =Test      # CMN(immediate)
 | 1100x      -        =DataProc  # ORR(immediate)
 | 1101x      -        =DataProc  # MOV(immediate)
                         # Note: The following instruction is used to mask
                         # memory addresses.
 | 1110x      -        = MaskedBinary2RegisterImmediateOp => ImmediateBic
                            Bic_Rule_19_A1_P50
                            cccc0011110unnnnddddiiiiiiiiiiii
-                           RdCanBePcAndNotRdIsPcAndS
+                           NotRdIsPcAndS
 | 1111x      -        =DataProc  # MVN(immediate)
 +--
 
 +-- mult (See Section A5.2.5)
 | op(23:20)
 | 000x      =Multiply          # MUL
 | 001x      =Multiply          # MLA
 | 0100      =LongMultiply(v6)  # UMAAL
 | 0101      =Undefined
 | 0110      =Multiply(v6T2)    # MLS
@@ skipping 515 matching lines @@
 | "     1001    "
 | "     1101    =VectorLoad  # VLD2(single, all lanes)
 | "     0x10    =VectorLoad  # VLD3(single)
 | "     1010    "
 | "     1110    =VectorLoad  # VLD3(single, all lanes)
 | "     0x11    =VectorLoad  # VLD4(single)
 | "     1011    "
 | "     1111    =VectorLoad  # VLD4(single, all lanes)
 | else:         =Undefined   # Note on page A7-27
 +--