Clean up code to clarify we are only tracking the condition flags of APSR.

src/trusted/validator_arm/baseline_classes.cc

Index: src/trusted/validator_arm/baseline_classes.cc
===================================================================
--- src/trusted/validator_arm/baseline_classes.cc	(revision 8564)
+++ src/trusted/validator_arm/baseline_classes.cc	(working copy)
@@ -24,7 +24,7 @@
 }
 
 RegisterList Unary1RegisterImmediateOp::defs(const Instruction i) const {
-  return d.reg(i) + flags.reg_if_updated(i);
+  return d.reg(i) + conditions.conds_if_updated(i);
 }
 
 // Binary2RegisterImmediateOp
@@ -35,7 +35,7 @@
 }
 
 RegisterList Binary2RegisterImmediateOp::defs(Instruction i) const {
-  return d.reg(i) + flags.reg_if_updated(i);
+  return d.reg(i) + conditions.conds_if_updated(i);
 }
 
 // TODO(karl): find out why we added this so that we allowed an
@@ -58,7 +58,7 @@
 }
 
 RegisterList BinaryRegisterImmediateTest::defs(Instruction i) const {
-  return flags.reg_if_updated(i);
+  return conditions.conds_if_updated(i);
 }
 
 // MaskedBinaryRegisterImmediateTest
@@ -66,7 +66,7 @@
     Instruction i, Register r, uint32_t mask) const {
   return n.reg(i) == r &&
       (imm.get_modified_immediate(i) & mask) == mask &&
-      defs(i)[kRegisterFlags];
+      defs(i)[kConditions];
 }
 
 // Unary2RegisterOp
@@ -77,7 +77,7 @@
 }
 
 RegisterList Unary2RegisterOp::defs(const Instruction i) const {
-  return d.reg(i) + flags.reg_if_updated(i);
+  return d.reg(i) + conditions.conds_if_updated(i);
 }
 
 // Binary3RegisterOp
@@ -92,7 +92,7 @@
 }
 
 RegisterList Binary3RegisterOp::defs(const Instruction i) const {
-  return d.reg(i) + flags.reg_if_updated(i);
+  return d.reg(i) + conditions.conds_if_updated(i);
 }
 
 // Unary2RegisterImmedShiftedOp
@@ -103,7 +103,7 @@
 }
 
 RegisterList Unary2RegisterImmedShiftedOp::defs(const Instruction i) const {
-  return d.reg(i) + flags.reg_if_updated(i);
+  return d.reg(i) + conditions.conds_if_updated(i);
 }
 
 // Unary3RegisterShiftedOp
@@ -117,7 +117,7 @@
 }
 
 RegisterList Unary3RegisterShiftedOp::defs(const Instruction i) const {
-  return d.reg(i) + flags.reg_if_updated(i);
+  return d.reg(i) + conditions.conds_if_updated(i);
 }
 
 // Binary3RegisterImmedShiftedOp
@@ -128,7 +128,7 @@
 }
 
 RegisterList Binary3RegisterImmedShiftedOp::defs(const Instruction i) const {
-  return d.reg(i) + flags.reg_if_updated(i);
+  return d.reg(i) + conditions.conds_if_updated(i);
 }
 
 // Binary4RegisterShiftedOp
@@ -143,7 +143,7 @@
 }
 
 RegisterList Binary4RegisterShiftedOp::defs(const Instruction i) const {
-  return d.reg(i) + flags.reg_if_updated(i);
+  return d.reg(i) + conditions.conds_if_updated(i);
 }
 
 // Binary2RegisterImmedShiftedTest
@@ -153,7 +153,7 @@
 }
 
 RegisterList Binary2RegisterImmedShiftedTest::defs(const Instruction i) const {
-  return flags.reg_if_updated(i);
+  return conditions.conds_if_updated(i);
 }
 
 // Binary3RegisterShiftedTest
@@ -164,7 +164,7 @@
 }
 
 RegisterList Binary3RegisterShiftedTest::defs(const Instruction i) const {
-  return flags.reg_if_updated(i);
+  return conditions.conds_if_updated(i);
 }
 
 }  // namespace