Clean up code to clarify we are only tracking the condition flags of APSR.

src/trusted/validator_arm/baseline_classes.h

 /*
  * Copyright (c) 2012 The Native Client Authors. All rights reserved.
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 #ifndef NATIVE_CLIENT_SRC_TRUSTED_VALIDATOR_ARM_BASELINE_CLASSES_H_
 #define NATIVE_CLIENT_SRC_TRUSTED_VALIDATOR_ARM_BASELINE_CLASSES_H_
 
 #include "native_client/src/trusted/validator_arm/inst_classes.h"
@@ skipping 33 matching lines @@
 // NaCl disallows writing to PC to cause a jump.
 //
 // Implements:
 //    MOV (immediate) A2 A8-194
 class Unary1RegisterImmediateOp : public ClassDecoder {
  public:
   // Interfaces for components in the instruction.
   static const Imm12Bits0To11Interface imm12;
   static const RegDBits12To15Interface d;
   static const Imm4Bits16To19Interface imm4;
-  static const UpdatesFlagsRegisterBit20Interface flags;
+  static const UpdatesConditionsBit20Interface conditions;
   static const ConditionBits28To31Interface cond;
 
   // Methods for class.
   inline Unary1RegisterImmediateOp() : ClassDecoder() {}
   virtual ~Unary1RegisterImmediateOp() {}
   virtual SafetyLevel safety(Instruction i) const;
   virtual RegisterList defs(Instruction i) const;
 
   // The immediate value stored in the instruction.
   inline uint32_t ImmediateValue(const Instruction& i) const {
@@ skipping 16 matching lines @@
 //    Rn = The first operand register.
 //    const = The immediate value to be used as the second argument.
 //
 // NaCl disallows writing to PC to cause a jump.
 class Binary2RegisterImmediateOp : public ClassDecoder {
  public:
   // Interfaces for components in the instruction.
   static const Imm12Bits0To11Interface imm;
   static const RegDBits12To15Interface d;
   static const RegNBits16To19Interface n;
-  static const UpdatesFlagsRegisterBit20Interface flags;
+  static const UpdatesConditionsBit20Interface conditions;
   static const ConditionBits28To31Interface cond;
 
   // Methods for class.
   inline Binary2RegisterImmediateOp() : ClassDecoder() {}
   virtual ~Binary2RegisterImmediateOp() {}
   virtual SafetyLevel safety(Instruction i) const;
   virtual RegisterList defs(Instruction i) const;
 
  private:
   NACL_DISALLOW_COPY_AND_ASSIGN(Binary2RegisterImmediateOp);
@@ skipping 29 matching lines @@
 // Implements:
 //    CMN(immediate) A1 A8-74
 //    CMP(immediate) A1 A8-80
 //    TEQ(immediate) A1 A8-448
 //    TST(immediate) A1 A8-454 - Note: See class TestImmediate.
 class BinaryRegisterImmediateTest : public ClassDecoder {
  public:
   // Interfaces for components in the instruction.
   static const Imm12Bits0To11Interface imm;
   static const RegNBits16To19Interface n;
-  static const UpdatesFlagsRegisterBit20Interface flags;
+  static const UpdatesConditionsBit20Interface conditions;
   static const ConditionBits28To31Interface cond;
 
   // Methods for class.
   inline BinaryRegisterImmediateTest() : ClassDecoder() {}
   virtual ~BinaryRegisterImmediateTest() {}
   virtual SafetyLevel safety(Instruction i) const;
   virtual RegisterList defs(Instruction i) const;
 
  private:
   NACL_DISALLOW_COPY_AND_ASSIGN(BinaryRegisterImmediateTest);
@@ skipping 27 matching lines @@
 // NaCl disallows writing to PC to cause a jump.
 //
 // Implements:
 //    MOV(register) A1 A8-196 - Shouldn't parse when Rd=15 and S=1;
 //    RRX A1 A8-282
 class Unary2RegisterOp : public ClassDecoder {
  public:
   // Interfaces for components in the instruction.
   static const RegMBits0To3Interface m;
   static const RegDBits12To15Interface d;
-  static const UpdatesFlagsRegisterBit20Interface flags;
+  static const UpdatesConditionsBit20Interface conditions;
   static const ConditionBits28To31Interface cond;
 
   // Methods for class.
   inline Unary2RegisterOp() : ClassDecoder() {}
   virtual ~Unary2RegisterOp() {}
   virtual SafetyLevel safety(Instruction i) const;
   virtual RegisterList defs(Instruction i) const;
 
  private:
   NACL_DISALLOW_COPY_AND_ASSIGN(Unary2RegisterOp);
@@ skipping 19 matching lines @@
 //    ASR(register) A1 A8-42
 //    LSL(register) A1 A8-180
 //    LSR(register) A1 A8-184
 //    ROR(register) A1 A8-280
 class Binary3RegisterOp : public ClassDecoder {
  public:
   // Interfaces for components in the instruction.
   static const RegNBits0To3Interface n;
   static const RegMBits8To11Interface m;
   static const RegDBits12To15Interface d;
-  static const UpdatesFlagsRegisterBit20Interface flags;
+  static const UpdatesConditionsBit20Interface conditions;
   static const ConditionBits28To31Interface cond;
 
   // Methods for class.
   inline Binary3RegisterOp() : ClassDecoder() {}
   virtual ~Binary3RegisterOp() {}
   virtual SafetyLevel safety(Instruction i) const;
   virtual RegisterList defs(Instruction i) const;
 
  private:
   NACL_DISALLOW_COPY_AND_ASSIGN(Binary3RegisterOp);
@@ skipping 19 matching lines @@
 //    LSR(immediate) A1 A8-182
 //    MVN(register) A8-216     -- Shouldn't parse when Rd=15 and S=1.
 //    ROR(immediate) A1 A8-278 -- Shouldn't parse when imm5=0.
 class Unary2RegisterImmedShiftedOp : public ClassDecoder {
  public:
   // Interfaces for components in the instruction.
   static const RegMBits0To3Interface m;
   static const ShiftTypeBits5To6Interface shift_type;
   static const Imm5Bits7To11Interface imm;
   static const RegDBits12To15Interface d;
-  static const UpdatesFlagsRegisterBit20Interface flags;
+  static const UpdatesConditionsBit20Interface conditions;
   static const ConditionBits28To31Interface cond;
 
   // Methods for class.
   inline Unary2RegisterImmedShiftedOp() : ClassDecoder() {}
   virtual ~Unary2RegisterImmedShiftedOp() {}
   virtual SafetyLevel safety(Instruction i) const;
   virtual RegisterList defs(Instruction i) const;
 
   // The immediate value stored in the instruction.
   inline uint32_t ImmediateValue(const Instruction& i) const {
@@ skipping 23 matching lines @@
 //
 // Implements:
 //    MVN(register-shifted) A1 A8-218
 class Unary3RegisterShiftedOp : public ClassDecoder {
  public:
   // Interfaces for components in the instruction.
   static const RegMBits0To3Interface m;
   static const ShiftTypeBits5To6Interface shift_type;
   static const RegSBits8To11Interface s;
   static const RegDBits12To15Interface d;
-  static const UpdatesFlagsRegisterBit20Interface flags;
+  static const UpdatesConditionsBit20Interface conditions;
   static const ConditionBits28To31Interface cond;
 
   // Methods for class.
   inline Unary3RegisterShiftedOp() : ClassDecoder() {}
   virtual ~Unary3RegisterShiftedOp() {}
   virtual SafetyLevel safety(Instruction i) const;
   virtual RegisterList defs(Instruction i) const;
 
  private:
   NACL_DISALLOW_COPY_AND_ASSIGN(Unary3RegisterShiftedOp);
@@ skipping 26 matching lines @@
 //    SBC(register) A1 A8-304 -- Shouldn't parse when Rd=15 and S=1.
 //    SUB(register) A1 A8-422 -- Shouldn't parse when Rd=15 and S=1, or Rn=13.
 class Binary3RegisterImmedShiftedOp : public ClassDecoder {
  public:
   // Interfaces for components in the instruction.
   static const RegMBits0To3Interface m;
   static const ShiftTypeBits5To6Interface shift_type;
   static const Imm5Bits7To11Interface imm;
   static const RegDBits12To15Interface d;
   static const RegNBits16To19Interface n;
-  static const UpdatesFlagsRegisterBit20Interface flags;
+  static const UpdatesConditionsBit20Interface conditions;
   static const ConditionBits28To31Interface cond;
 
   // Methods for class.
   inline Binary3RegisterImmedShiftedOp() : ClassDecoder() {}
   virtual ~Binary3RegisterImmedShiftedOp() {}
   virtual SafetyLevel safety(Instruction i) const;
   virtual RegisterList defs(Instruction i) const;
   // The shift value to use.
   inline uint32_t ShiftValue(const Instruction& i) const {
     return shift_type.DecodeImmShift(i, imm.value(i));
@@ skipping 31 matching lines @@
 //    RSC(register-shifted) A1 A8-294
 //    SBC(register-shifted) A1 A8-306
 //    SUB(register-shifted) A1 A8-424
 class Binary4RegisterShiftedOp : public ClassDecoder {
  public:
   // Interfaces for components in the instruction.
   static const RegMBits0To3Interface m;
   static const RegSBits8To11Interface s;
   static const RegDBits12To15Interface d;
   static const RegNBits16To19Interface n;
-  static const UpdatesFlagsRegisterBit20Interface flags;
+  static const UpdatesConditionsBit20Interface conditions;
   static const ConditionBits28To31Interface cond;
 
   // Methods for class.
   inline Binary4RegisterShiftedOp() : ClassDecoder() {}
   virtual ~Binary4RegisterShiftedOp() {}
   virtual SafetyLevel safety(Instruction i) const;
   virtual RegisterList defs(Instruction i) const;
 
  private:
   NACL_DISALLOW_COPY_AND_ASSIGN(Binary4RegisterShiftedOp);
@@ skipping 16 matching lines @@
 //    CMP(register) A1 A8-82
 //    TEQ(register) A1 A8-450
 //    TST(register) A1 A8-456
 class Binary2RegisterImmedShiftedTest : public ClassDecoder {
  public:
   // Interfaces for components in the instruction.
   static const RegMBits0To3Interface m;
   static const ShiftTypeBits5To6Interface shift_type;
   static const Imm5Bits7To11Interface imm;
   static const RegNBits16To19Interface n;
-  static const UpdatesFlagsRegisterBit20Interface flags;
+  static const UpdatesConditionsBit20Interface conditions;
   static const ConditionBits28To31Interface cond;
 
   // Methods for class.
   inline Binary2RegisterImmedShiftedTest() : ClassDecoder() {}
   virtual ~Binary2RegisterImmedShiftedTest() {}
   virtual SafetyLevel safety(Instruction i) const;
   virtual RegisterList defs(Instruction i) const;
   // The shift value to use.
   inline uint32_t ShiftValue(const Instruction& i) const {
     return shift_type.DecodeImmShift(i, imm.value(i));
@@ skipping 24 matching lines @@
 //    CMP(register-shifted) A1 A8-84
 //    TEQ(register-shifted) A1 A8-452
 //    TST(register-shifted) A1 A8-458
 class Binary3RegisterShiftedTest : public ClassDecoder {
  public:
   // Interfaces for components in the instruction.
   static const RegMBits0To3Interface m;
   static const ShiftTypeBits5To6Interface shift_type;
   static const RegSBits8To11Interface s;
   static const RegNBits16To19Interface n;
-  static const UpdatesFlagsRegisterBit20Interface flags;
+  static const UpdatesConditionsBit20Interface conditions;
   static const ConditionBits28To31Interface cond;
 
   // Methods for class.
   inline Binary3RegisterShiftedTest() : ClassDecoder() {}
   virtual ~Binary3RegisterShiftedTest() {}
   virtual SafetyLevel safety(Instruction i) const;
   virtual RegisterList defs(Instruction i) const;
 
  private:
   NACL_DISALLOW_COPY_AND_ASSIGN(Binary3RegisterShiftedTest);
 };
 
 }  // namespace
 
 #endif  // NATIVE_CLIENT_SRC_TRUSTED_VALIDATOR_ARM_BASELINE_CLASSES_H_