Clean up code to clarify we are only tracking the condition flags of APSR.

src/trusted/validator_arm/actual_classes.h

 /*
  * Copyright (c) 2012 The Native Client Authors. All rights reserved.
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 #ifndef NATIVE_CLIENT_SRC_TRUSTED_VALIDATOR_ARM_ACTUAL_CLASSES_H_
 #define NATIVE_CLIENT_SRC_TRUSTED_VALIDATOR_ARM_ACTUAL_CLASSES_H_
 
 #include "native_client/src/trusted/validator_arm/inst_classes.h"
@@ skipping 15 matching lines @@
  *
  * TODO(karl): finish updating this file to match what we want for the
  *             arm validator.
  */
 namespace nacl_arm_dec {
 
 // **************************************************************
 //      N E W    C L A S S    D E C O D E R S
 // **************************************************************
 
+// Data processing and arithmetic
 class Defs12To15 : public ClassDecoder {
  public:
   inline Defs12To15() : ClassDecoder() {}
   virtual ~Defs12To15() {}
 
   // We use Rd to capture the register being set.
   static const RegDBits12To15Interface d;
-  static const UpdatesFlagsRegisterBit20Interface flags;
+  static const UpdatesConditionsBit20Interface conditions;
 
   virtual SafetyLevel safety(Instruction i) const;
   virtual RegisterList defs(Instruction i) const;
 
  private:
   NACL_DISALLOW_COPY_AND_ASSIGN(Defs12To15);
 };
 
 // Defs12To15 where registers Rn, Rd, Rs, and Rm are not Pc.
+// Note: Some instructions may use other names for the registers,
+// but they have the same placement within the instruction, and
+// hence do not need a separate class decoder.
 class Defs12To15RdRnRsRmNotPc : public Defs12To15 {
  public:
   static const RegMBits0To3Interface m;
   static const RegSBits8To11Interface s;
   static const RegNBits16To19Interface n;
 
   inline Defs12To15RdRnRsRmNotPc() : Defs12To15() {}
   virtual ~Defs12To15RdRnRsRmNotPc() {}
 
   virtual SafetyLevel safety(Instruction i) const;
+
+ private:
+  NACL_DISALLOW_COPY_AND_ASSIGN(Defs12To15RdRnRsRmNotPc);
 };
 
 // **************************************************************
 //      O L D    C L A S S    D E C O D E R S
 // **************************************************************
 
 class OldClassDecoder : public ClassDecoder {
  public:
   inline OldClassDecoder() : ClassDecoder() {}
   virtual ~OldClassDecoder() {}
 
   // Many instructions define control bits in bits 20-24. The useful bits
   // are defined here.
 
-  // True if U (updates flags register) flag is defined.
-  inline bool UpdatesFlagsRegister(const Instruction& i) const {
+  // True if S (updates condition flags in APSR register) flag is defined.
+  inline bool UpdatesConditions(const Instruction& i) const {
     return i.bit(20);
   }
 
   // True if W (does write) flag is defined.
   inline bool WritesFlag(const Instruction& i) const {
     return i.bit(21);
   }
   // True if P (pre-indexing) flag is defined.
   inline bool PreindexingFlag(const Instruction& i) const {
     return i.bit(24);
@@ skipping 724 matching lines @@
  public:
   inline MoveFromCoprocessor() {}
   virtual ~MoveFromCoprocessor() {}
 
   virtual RegisterList defs(Instruction i) const;
   // Defines the destination core register.
   inline Register Rt(const Instruction& i) const {
     Register rt = i.reg(15, 12);
     if (rt == kRegisterPc) {
       // Per ARM ISA spec: r15 here is a synonym for the flags register!
-      return kRegisterFlags;
+      return kConditions;
     }
     return rt;
   }
 
  private:
   NACL_DISALLOW_COPY_AND_ASSIGN(MoveFromCoprocessor);
 };
 
 // MRRC/MRRC2, which load pairs of registers from a coprocessor register.
 class MoveDoubleFromCoprocessor : public CoprocessorOp {
@@ skipping 63 matching lines @@
   }
   virtual int32_t branch_target_offset(Instruction i) const;
 
  private:
   NACL_DISALLOW_COPY_AND_ASSIGN(Branch);
 };
 
 }  // namespace
 
 #endif  // NATIVE_CLIENT_SRC_TRUSTED_VALIDATOR_ARM_ACTUAL_CLASSES_H_