Clean up code to clarify we are only tracking the condition flags of APSR.

src/trusted/validator_arm/inst_classes_testers.cc

 /*
  * Copyright (c) 2012 The Native Client Authors. All rights reserved.
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 #ifndef NACL_TRUSTED_BUT_NOT_TCB
 #error This file is not meant for use in the TCB
 #endif
 
 #include "native_client/src/trusted/validator_arm/inst_classes_testers.h"
 
 #include "gtest/gtest.h"
 #include "native_client/src/trusted/validator_arm/decoder_tester.h"
 
-using nacl_arm_dec::kRegisterFlags;
+using nacl_arm_dec::kConditions;
 using nacl_arm_dec::kRegisterNone;
 using nacl_arm_dec::kRegisterPc;
 using nacl_arm_dec::kRegisterStack;
 using nacl_arm_dec::Instruction;
 
 namespace nacl_arm_test {
 
 // Unary1RegisterImmediateOpTester
 Unary1RegisterImmediateOpTester::Unary1RegisterImmediateOpTester(
     const NamedClassDecoder& decoder)
@@ skipping 10 matching lines @@
   // Didn't parse undefined conditional.
   if (expected_decoder.cond.undefined(inst)) {
     NC_EXPECT_NE_PRECOND(&ExpectedDecoder(), &decoder);
   }
 
   // Check if expected class name found.
   NC_PRECOND(Arm32DecoderTester::ApplySanityChecks(inst, decoder));
 
   // Check Registers and flags used in DataProc.
   EXPECT_EQ(expected_decoder.d.number(inst), inst.bits(15, 12));
-  EXPECT_EQ(expected_decoder.flags.is_updated(inst), inst.bit(20));
-  if (expected_decoder.flags.is_updated(inst)) {
-    EXPECT_EQ(expected_decoder.flags.reg_if_updated(inst), kRegisterFlags);
+  EXPECT_EQ(expected_decoder.conditions.is_updated(inst), inst.bit(20));
+  if (expected_decoder.conditions.is_updated(inst)) {
+    EXPECT_EQ(expected_decoder.conditions.conds_if_updated(inst), kConditions);
   } else {
-    EXPECT_EQ(expected_decoder.flags.reg_if_updated(inst), kRegisterNone);
+    EXPECT_EQ(expected_decoder.conditions.conds_if_updated(inst),
+              kRegisterNone);
   }
 
   // Check that immediate value is computed correctly.
   EXPECT_EQ(expected_decoder.imm4.value(inst), inst.bits(19, 16));
   EXPECT_EQ(expected_decoder.imm12.value(inst), inst.bits(11, 0));
   EXPECT_EQ(expected_decoder.ImmediateValue(inst),
             (inst.bits(19, 16) << 12) | inst.bits(11, 0));
   EXPECT_LT(expected_decoder.ImmediateValue(inst), (uint32_t) 0x10000);
 
   // Other NaCl constraints about this instruction.
@@ skipping 29 matching lines @@
     const NamedClassDecoder& decoder)
     : Unary1RegisterImmediateOpTester(decoder) {}
 
 bool Unary1RegisterImmediateOpTesterNotRdIsPcAndS::
 ApplySanityChecks(Instruction inst,
                   const NamedClassDecoder& decoder) {
   nacl_arm_dec::Unary1RegisterImmediateOp expected_decoder;
 
   // Check that we don't parse when Rd=15 and S=1.
   if ((expected_decoder.d.reg(inst) == kRegisterPc) &&
-      expected_decoder.flags.is_updated(inst)) {
+      expected_decoder.conditions.is_updated(inst)) {
     NC_EXPECT_NE_PRECOND(&ExpectedDecoder(), &decoder);
   }
 
   return Unary1RegisterImmediateOpTester::ApplySanityChecks(inst, decoder);
 }
 
 // Binary2RegisterImmediateOpTester
 Binary2RegisterImmediateOpTester::Binary2RegisterImmediateOpTester(
     const NamedClassDecoder& decoder)
     : Arm32DecoderTester(decoder), apply_rd_is_pc_check_(true) {}
@@ skipping 10 matching lines @@
   if (expected_decoder.cond.undefined(inst)) {
     NC_EXPECT_NE_PRECOND(&ExpectedDecoder(), &decoder);
   }
 
   // Check if expected class name found.
   NC_PRECOND(Arm32DecoderTester::ApplySanityChecks(inst, decoder));
 
   // Check Registers and flags used in DataProc.
   EXPECT_EQ(expected_decoder.n.number(inst), inst.bits(19, 16));
   EXPECT_EQ(expected_decoder.d.number(inst), inst.bits(15, 12));
-  EXPECT_EQ(expected_decoder.flags.is_updated(inst), inst.bit(20));
-  if (expected_decoder.flags.is_updated(inst)) {
-    EXPECT_EQ(expected_decoder.flags.reg_if_updated(inst), kRegisterFlags);
+  EXPECT_EQ(expected_decoder.conditions.is_updated(inst), inst.bit(20));
+  if (expected_decoder.conditions.is_updated(inst)) {
+    EXPECT_EQ(expected_decoder.conditions.conds_if_updated(inst), kConditions);
   } else {
-    EXPECT_EQ(expected_decoder.flags.reg_if_updated(inst), kRegisterNone);
+    EXPECT_EQ(expected_decoder.conditions.conds_if_updated(inst),
+              kRegisterNone);
   }
 
   // Check that immediate value is computed correctly.
   EXPECT_EQ(expected_decoder.imm.value(inst), inst.bits(11, 0));
 
   // Other NaCl constraints about this instruction.
   if (apply_rd_is_pc_check_) {
     EXPECT_NE(expected_decoder.d.number(inst), (uint32_t) 15)
         << "Expected FORBIDDEN_OPERANDS for " << InstContents();
   }
 
   return true;
 }
 
 // Binary2RegisterImmediateOpTesterNotRdIsPcAndS
 Binary2RegisterImmediateOpTesterNotRdIsPcAndS::
 Binary2RegisterImmediateOpTesterNotRdIsPcAndS(
     const NamedClassDecoder& decoder)
     : Binary2RegisterImmediateOpTester(decoder) {}
 
 bool Binary2RegisterImmediateOpTesterNotRdIsPcAndS::
 ApplySanityChecks(Instruction inst,
                   const NamedClassDecoder& decoder) {
   nacl_arm_dec::Binary2RegisterImmediateOp expected_decoder;
 
   // Check that we don't parse when Rd=15 and S=1.
   if ((expected_decoder.d.reg(inst) == kRegisterPc) &&
-      expected_decoder.flags.is_updated(inst)) {
+      expected_decoder.conditions.is_updated(inst)) {
     NC_EXPECT_NE_PRECOND(&ExpectedDecoder(), &decoder);
   }
 
   return Binary2RegisterImmediateOpTester::ApplySanityChecks(inst, decoder);
 }
 
 // Binary2RegisterImmediateOpTesterRdCanBePcAndNotRdIsPcAndS
 Binary2RegisterImmediateOpTesterRdCanBePcAndNotRdIsPcAndS::
 Binary2RegisterImmediateOpTesterRdCanBePcAndNotRdIsPcAndS(
     const NamedClassDecoder& decoder)
@@ skipping 17 matching lines @@
   // Didn't parse undefined conditional.
   if (expected_decoder.cond.undefined(inst)) {
     NC_EXPECT_NE_PRECOND(&ExpectedDecoder(), &decoder);
   }
 
   // Check if expected class name found.
   NC_PRECOND(Arm32DecoderTester::ApplySanityChecks(inst, decoder));
 
   // Check Registers and flags used in DataProc.
   EXPECT_EQ(expected_decoder.n.number(inst), inst.bits(19, 16));
-  EXPECT_EQ(expected_decoder.flags.is_updated(inst), inst.bit(20));
-  if (expected_decoder.flags.is_updated(inst)) {
-    EXPECT_EQ(expected_decoder.flags.reg_if_updated(inst), kRegisterFlags);
+  EXPECT_EQ(expected_decoder.conditions.is_updated(inst), inst.bit(20));
+  if (expected_decoder.conditions.is_updated(inst)) {
+    EXPECT_EQ(expected_decoder.conditions.conds_if_updated(inst), kConditions);
   } else {
-    EXPECT_EQ(expected_decoder.flags.reg_if_updated(inst), kRegisterNone);
+    EXPECT_EQ(expected_decoder.conditions.conds_if_updated(inst),
+              kRegisterNone);
   }
 
   // Check that immediate value is computed correctly.
   EXPECT_EQ(expected_decoder.imm.value(inst), inst.bits(11, 0));
 
   return true;
 }
 
 // Unary2RegisterOpTester
 Unary2RegisterOpTester::Unary2RegisterOpTester(
@@ skipping 12 matching lines @@
   if (expected_decoder.cond.undefined(inst)) {
     NC_EXPECT_NE_PRECOND(&ExpectedDecoder(), &decoder);
   }
 
   // Check if expected class name found.
   NC_PRECOND(!Arm32DecoderTester::ApplySanityChecks(inst, decoder));
 
   // Check Registers and flags used in DataProc.
   EXPECT_EQ(expected_decoder.d.number(inst), inst.bits(15, 12));
   EXPECT_EQ(expected_decoder.m.number(inst), inst.bits(3, 0));
-  EXPECT_EQ(expected_decoder.flags.is_updated(inst), inst.bit(20));
-  if (expected_decoder.flags.is_updated(inst)) {
-    EXPECT_EQ(expected_decoder.flags.reg_if_updated(inst), kRegisterFlags);
+  EXPECT_EQ(expected_decoder.conditions.is_updated(inst), inst.bit(20));
+  if (expected_decoder.conditions.is_updated(inst)) {
+    EXPECT_EQ(expected_decoder.conditions.conds_if_updated(inst), kConditions);
   } else {
-    EXPECT_EQ(expected_decoder.flags.reg_if_updated(inst), kRegisterNone);
+    EXPECT_EQ(expected_decoder.conditions.conds_if_updated(inst),
+              kRegisterNone);
   }
 
   // Other NaCl constraints about this instruction.
   EXPECT_NE(expected_decoder.d.number(inst), (uint32_t) 15)
       << "Expected FORBIDDEN_OPERANDS for " << InstContents();
 
   return true;
 }
 
 // Unary2RegisterOpTesterNotRdIsPcAndS
 Unary2RegisterOpTesterNotRdIsPcAndS::Unary2RegisterOpTesterNotRdIsPcAndS(
     const NamedClassDecoder& decoder)
     : Unary2RegisterOpTester(decoder) {}
 
 
 bool Unary2RegisterOpTesterNotRdIsPcAndS::
 ApplySanityChecks(Instruction inst,
                   const NamedClassDecoder& decoder) {
   nacl_arm_dec::Unary2RegisterOp expected_decoder;
 
   // Check that we don't parse when Rd=15 and S=1.
   if ((expected_decoder.d.reg(inst) == kRegisterPc) &&
-      expected_decoder.flags.is_updated(inst)) {
+      expected_decoder.conditions.is_updated(inst)) {
     NC_EXPECT_NE_PRECOND(&ExpectedDecoder(), &decoder);
   }
 
   return Unary2RegisterOpTester::ApplySanityChecks(inst, decoder);
 }
 
 // Binary3RegisterOpTester
 Binary3RegisterOpTester::Binary3RegisterOpTester(
     const NamedClassDecoder& decoder)
     : Arm32DecoderTester(decoder) {}
@@ skipping 11 matching lines @@
     NC_EXPECT_NE_PRECOND(&ExpectedDecoder(), &decoder);
   }
 
   // Check if expected class name found.
   NC_PRECOND(Arm32DecoderTester::ApplySanityChecks(inst, decoder));
 
   // Check Registers and flags used in DataProc.
   EXPECT_EQ(expected_decoder.d.number(inst), inst.bits(15, 12));
   EXPECT_EQ(expected_decoder.m.number(inst), inst.bits(11, 8));
   EXPECT_EQ(expected_decoder.n.number(inst), inst.bits(3, 0));
-  EXPECT_EQ(expected_decoder.flags.is_updated(inst), inst.bit(20));
-  if (expected_decoder.flags.is_updated(inst)) {
-    EXPECT_EQ(expected_decoder.flags.reg_if_updated(inst), kRegisterFlags);
+  EXPECT_EQ(expected_decoder.conditions.is_updated(inst), inst.bit(20));
+  if (expected_decoder.conditions.is_updated(inst)) {
+    EXPECT_EQ(expected_decoder.conditions.conds_if_updated(inst), kConditions);
   } else {
-    EXPECT_EQ(expected_decoder.flags.reg_if_updated(inst), kRegisterNone);
+    EXPECT_EQ(expected_decoder.conditions.conds_if_updated(inst),
+              kRegisterNone);
   }
 
   // Other NaCl constraints about this instruction.
   EXPECT_NE(expected_decoder.d.number(inst), (uint32_t) 15)
       << "Expected FORBIDDEN_OPERANDS for " << InstContents();
 
   return true;
 }
 
 // Binary3RegisterOpTesterRegsNotPc
@@ skipping 36 matching lines @@
   if (expected_decoder.cond.undefined(inst)) {
     NC_EXPECT_NE_PRECOND(&ExpectedDecoder(), &decoder);
   }
 
   // Check if expected class name found.
   NC_PRECOND(Arm32DecoderTester::ApplySanityChecks(inst, decoder));
 
   // Check Registers and flags used in DataProc.
   EXPECT_EQ(expected_decoder.d.number(inst), inst.bits(15, 12));
   EXPECT_EQ(expected_decoder.m.number(inst), inst.bits(3, 0));
-  EXPECT_EQ(expected_decoder.flags.is_updated(inst), inst.bit(20));
-  if (expected_decoder.flags.is_updated(inst)) {
-    EXPECT_EQ(expected_decoder.flags.reg_if_updated(inst), kRegisterFlags);
+  EXPECT_EQ(expected_decoder.conditions.is_updated(inst), inst.bit(20));
+  if (expected_decoder.conditions.is_updated(inst)) {
+    EXPECT_EQ(expected_decoder.conditions.conds_if_updated(inst), kConditions);
   } else {
-    EXPECT_EQ(expected_decoder.flags.reg_if_updated(inst), kRegisterNone);
+    EXPECT_EQ(expected_decoder.conditions.conds_if_updated(inst),
+              kRegisterNone);
   }
 
   // Check that immediate value is computed correctly.
   EXPECT_EQ(expected_decoder.imm.value(inst), inst.bits(11, 7));
   EXPECT_EQ(expected_decoder.shift_type.value(inst), inst.bits(6, 5));
 
   // Other NaCl constraints about this instruction.
   EXPECT_NE(expected_decoder.d.number(inst), (uint32_t) 15)
       << "Expected FORBIDDEN_OPERANDS for " << InstContents();
 
@@ skipping 25 matching lines @@
     const NamedClassDecoder& decoder)
     : Unary2RegisterImmedShiftedOpTester(decoder) {}
 
 bool Unary2RegisterImmedShiftedOpTesterNotRdIsPcAndS::
 ApplySanityChecks(Instruction inst,
                   const NamedClassDecoder& decoder) {
   nacl_arm_dec::Unary2RegisterImmedShiftedOp expected_decoder;
 
   // Check that we don't parse when Rd=15 and S=1.
   if ((expected_decoder.d.reg(inst) == kRegisterPc) &&
-      expected_decoder.flags.is_updated(inst)) {
+      expected_decoder.conditions.is_updated(inst)) {
     NC_EXPECT_NE_PRECOND(&ExpectedDecoder(), &decoder);
   }
 
   return Unary2RegisterImmedShiftedOpTester::ApplySanityChecks(inst, decoder);
 }
 
 // Unary3RegisterShiftedOpTester
 Unary3RegisterShiftedOpTester::Unary3RegisterShiftedOpTester(
     const NamedClassDecoder& decoder)
     : Arm32DecoderTester(decoder) {}
@@ skipping 11 matching lines @@
     NC_EXPECT_NE_PRECOND(&ExpectedDecoder(), &decoder);
   }
 
   // Check if expected class name found.
   NC_PRECOND(Arm32DecoderTester::ApplySanityChecks(inst, decoder));
 
   // Check Registers and flags used in DataProc.
   EXPECT_EQ(expected_decoder.d.number(inst), inst.bits(15, 12));
   EXPECT_EQ(expected_decoder.s.number(inst), inst.bits(11, 8));
   EXPECT_EQ(expected_decoder.m.number(inst), inst.bits(3, 0));
-  EXPECT_EQ(expected_decoder.flags.is_updated(inst), inst.bit(20));
-  if (expected_decoder.flags.is_updated(inst)) {
-    EXPECT_EQ(expected_decoder.flags.reg_if_updated(inst), kRegisterFlags);
+  EXPECT_EQ(expected_decoder.conditions.is_updated(inst), inst.bit(20));
+  if (expected_decoder.conditions.is_updated(inst)) {
+    EXPECT_EQ(expected_decoder.conditions.conds_if_updated(inst), kConditions);
   } else {
-    EXPECT_EQ(expected_decoder.flags.reg_if_updated(inst), kRegisterNone);
+    EXPECT_EQ(expected_decoder.conditions.conds_if_updated(inst),
+              kRegisterNone);
   }
 
   // Check the shift type.
   EXPECT_EQ(expected_decoder.shift_type.value(inst), inst.bits(6, 5));
 
   // Other NaCl constraints about this instruction.
   EXPECT_NE(expected_decoder.d.number(inst), (uint32_t) 15)
       << "Expected FORBIDDEN_OPERANDS for " << InstContents();
 
   return true;
@@ skipping 40 matching lines @@
     NC_EXPECT_NE_PRECOND(&ExpectedDecoder(), &decoder);
   }
 
   // Check if expected class name found.
   NC_PRECOND(Arm32DecoderTester::ApplySanityChecks(inst, decoder));
 
   // Check Registers and flags used in DataProc.
   EXPECT_EQ(expected_decoder.n.number(inst), inst.bits(19, 16));
   EXPECT_EQ(expected_decoder.d.number(inst), inst.bits(15, 12));
   EXPECT_EQ(expected_decoder.m.number(inst), inst.bits(3, 0));
-  EXPECT_EQ(expected_decoder.flags.is_updated(inst), inst.bit(20));
-  if (expected_decoder.flags.is_updated(inst)) {
-    EXPECT_EQ(expected_decoder.flags.reg_if_updated(inst), kRegisterFlags);
+  EXPECT_EQ(expected_decoder.conditions.is_updated(inst), inst.bit(20));
+  if (expected_decoder.conditions.is_updated(inst)) {
+    EXPECT_EQ(expected_decoder.conditions.conds_if_updated(inst), kConditions);
   } else {
-    EXPECT_EQ(expected_decoder.flags.reg_if_updated(inst), kRegisterNone);
+    EXPECT_EQ(expected_decoder.conditions.conds_if_updated(inst),
+              kRegisterNone);
   }
 
   // Check that immediate value is computed correctly.
   EXPECT_EQ(expected_decoder.imm.value(inst), inst.bits(11, 7));
   EXPECT_EQ(expected_decoder.shift_type.value(inst), inst.bits(6, 5));
 
   // Other NaCl constraints about this instruction.
   EXPECT_NE(expected_decoder.d.number(inst), (uint32_t) 15)
       << "Expected FORBIDDEN_OPERANDS for " << InstContents();
 
   return true;
 }
 
 // Binary3RegisterImmedShiftedOpTesterNotRdIsPcAndS
 Binary3RegisterImmedShiftedOpTesterNotRdIsPcAndS::
 Binary3RegisterImmedShiftedOpTesterNotRdIsPcAndS(
     const NamedClassDecoder& decoder)
     : Binary3RegisterImmedShiftedOpTester(decoder) {}
 
 bool Binary3RegisterImmedShiftedOpTesterNotRdIsPcAndS::
 ApplySanityChecks(Instruction inst,
                   const NamedClassDecoder& decoder) {
   nacl_arm_dec::Binary3RegisterImmedShiftedOp expected_decoder;
 
   // Check that we don't parse when Rd=15 and S=1.
   if ((expected_decoder.d.reg(inst) == kRegisterPc) &&
-      expected_decoder.flags.is_updated(inst)) {
+      expected_decoder.conditions.is_updated(inst)) {
     NC_EXPECT_NE_PRECOND(&ExpectedDecoder(), &decoder);
   }
 
   return Binary3RegisterImmedShiftedOpTester::ApplySanityChecks(inst, decoder);
 }
 
 // Binary4RegisterShiftedOpTester
 Binary4RegisterShiftedOpTester::Binary4RegisterShiftedOpTester(
     const NamedClassDecoder& decoder)
       : Arm32DecoderTester(decoder) {}
@@ skipping 12 matching lines @@
   }
 
   // Check if expected class name found.
   NC_PRECOND(Arm32DecoderTester::ApplySanityChecks(inst, decoder));
 
   // Check Registers and flags used in DataProc.
   EXPECT_EQ(expected_decoder.n.number(inst), inst.bits(19, 16));
   EXPECT_EQ(expected_decoder.d.number(inst), inst.bits(15, 12));
   EXPECT_EQ(expected_decoder.s.number(inst), inst.bits(11, 8));
   EXPECT_EQ(expected_decoder.m.number(inst), inst.bits(3, 0));
-  EXPECT_EQ(expected_decoder.flags.is_updated(inst), inst.bit(20));
-  if (expected_decoder.flags.is_updated(inst)) {
-    EXPECT_EQ(expected_decoder.flags.reg_if_updated(inst), kRegisterFlags);
+  EXPECT_EQ(expected_decoder.conditions.is_updated(inst), inst.bit(20));
+  if (expected_decoder.conditions.is_updated(inst)) {
+    EXPECT_EQ(expected_decoder.conditions.conds_if_updated(inst), kConditions);
   } else {
-    EXPECT_EQ(expected_decoder.flags.reg_if_updated(inst), kRegisterNone);
+    EXPECT_EQ(expected_decoder.conditions.conds_if_updated(inst),
+              kRegisterNone);
   }
 
   // Other NaCl constraints about this instruction.
   EXPECT_NE(expected_decoder.d.number(inst), (uint32_t) 15)
       << "Expected FORBIDDEN_OPERANDS for " << InstContents();
 
   return true;
 }
 
 // Binary4RegisterShiftedOpTesterRegsNotPc
@@ skipping 39 matching lines @@
   if (expected_decoder.cond.undefined(inst)) {
     NC_EXPECT_NE_PRECOND(&ExpectedDecoder(), &decoder);
   }
 
   // Check if expected class name found.
   NC_PRECOND(Arm32DecoderTester::ApplySanityChecks(inst, decoder));
 
   // Check Registers and flags used in DataProc.
   EXPECT_EQ(expected_decoder.n.number(inst), inst.bits(19, 16));
   EXPECT_EQ(expected_decoder.m.number(inst), inst.bits(3, 0));
-  EXPECT_EQ(expected_decoder.flags.is_updated(inst), inst.bit(20));
-  if (expected_decoder.flags.is_updated(inst)) {
-    EXPECT_EQ(expected_decoder.flags.reg_if_updated(inst), kRegisterFlags);
+  EXPECT_EQ(expected_decoder.conditions.is_updated(inst), inst.bit(20));
+  if (expected_decoder.conditions.is_updated(inst)) {
+    EXPECT_EQ(expected_decoder.conditions.conds_if_updated(inst), kConditions);
   } else {
-    EXPECT_EQ(expected_decoder.flags.reg_if_updated(inst), kRegisterNone);
+    EXPECT_EQ(expected_decoder.conditions.conds_if_updated(inst),
+              kRegisterNone);
   }
 
   // Check that immediate value is computed correctly.
   EXPECT_EQ(expected_decoder.imm.value(inst), inst.bits(11, 7));
   EXPECT_EQ(expected_decoder.shift_type.value(inst), inst.bits(6, 5));
 
   return true;
 }
 
 // Binary3RegisterShiftedTestTester
@@ skipping 14 matching lines @@
     NC_EXPECT_NE_PRECOND(&ExpectedDecoder(), &decoder);
   }
 
   // Check if expected class name found.
   NC_PRECOND(Arm32DecoderTester::ApplySanityChecks(inst, decoder));
 
   // Check Registers and flags used in DataProc.
   EXPECT_EQ(expected_decoder.n.number(inst), inst.bits(19, 16));
   EXPECT_EQ(expected_decoder.s.number(inst), inst.bits(11, 8));
   EXPECT_EQ(expected_decoder.m.number(inst), inst.bits(3, 0));
-  EXPECT_EQ(expected_decoder.flags.is_updated(inst), inst.bit(20));
-  if (expected_decoder.flags.is_updated(inst)) {
-    EXPECT_EQ(expected_decoder.flags.reg_if_updated(inst), kRegisterFlags);
+  EXPECT_EQ(expected_decoder.conditions.is_updated(inst), inst.bit(20));
+  if (expected_decoder.conditions.is_updated(inst)) {
+    EXPECT_EQ(expected_decoder.conditions.conds_if_updated(inst), kConditions);
   } else {
-    EXPECT_EQ(expected_decoder.flags.reg_if_updated(inst), kRegisterNone);
+    EXPECT_EQ(expected_decoder.conditions.conds_if_updated(inst),
+              kRegisterNone);
   }
   EXPECT_EQ(expected_decoder.shift_type.value(inst), inst.bits(6, 5));
 
   return true;
 }
 
 // Binary3RegisterShiftedTestTesterRegsNotPc
 Binary3RegisterShiftedTestTesterRegsNotPc::
 Binary3RegisterShiftedTestTesterRegsNotPc(
     const NamedClassDecoder& decoder)
@@ skipping 12 matching lines @@
       << "Expected Unpredictable for " << InstContents();
   EXPECT_NE(expected_decoder.s.number(inst), (uint32_t) 15)
       << "Expected Unpredictable for " << InstContents();
   EXPECT_NE(expected_decoder.m.number(inst), (uint32_t) 15)
       << "Expected Unpredictable for " << InstContents();
 
   return true;
 }
 
 }  // namespace