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1 // Copyright 2011 the V8 project authors. All rights reserved. | 1 // Copyright 2011 the V8 project authors. All rights reserved. |
2 // Redistribution and use in source and binary forms, with or without | 2 // Redistribution and use in source and binary forms, with or without |
3 // modification, are permitted provided that the following conditions are | 3 // modification, are permitted provided that the following conditions are |
4 // met: | 4 // met: |
5 // | 5 // |
6 // * Redistributions of source code must retain the above copyright | 6 // * Redistributions of source code must retain the above copyright |
7 // notice, this list of conditions and the following disclaimer. | 7 // notice, this list of conditions and the following disclaimer. |
8 // * Redistributions in binary form must reproduce the above | 8 // * Redistributions in binary form must reproduce the above |
9 // copyright notice, this list of conditions and the following | 9 // copyright notice, this list of conditions and the following |
10 // disclaimer in the documentation and/or other materials provided | 10 // disclaimer in the documentation and/or other materials provided |
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308 DisassemblerX64(const NameConverter& converter, | 308 DisassemblerX64(const NameConverter& converter, |
309 UnimplementedOpcodeAction unimplemented_action = | 309 UnimplementedOpcodeAction unimplemented_action = |
310 ABORT_ON_UNIMPLEMENTED_OPCODE) | 310 ABORT_ON_UNIMPLEMENTED_OPCODE) |
311 : converter_(converter), | 311 : converter_(converter), |
312 tmp_buffer_pos_(0), | 312 tmp_buffer_pos_(0), |
313 abort_on_unimplemented_( | 313 abort_on_unimplemented_( |
314 unimplemented_action == ABORT_ON_UNIMPLEMENTED_OPCODE), | 314 unimplemented_action == ABORT_ON_UNIMPLEMENTED_OPCODE), |
315 rex_(0), | 315 rex_(0), |
316 operand_size_(0), | 316 operand_size_(0), |
317 group_1_prefix_(0), | 317 group_1_prefix_(0), |
318 byte_size_operand_(false) { | 318 byte_size_operand_(false), |
| 319 instruction_table_(instruction_table.Pointer()) { |
319 tmp_buffer_[0] = '\0'; | 320 tmp_buffer_[0] = '\0'; |
320 } | 321 } |
321 | 322 |
322 virtual ~DisassemblerX64() { | 323 virtual ~DisassemblerX64() { |
323 } | 324 } |
324 | 325 |
325 // Writes one disassembled instruction into 'buffer' (0-terminated). | 326 // Writes one disassembled instruction into 'buffer' (0-terminated). |
326 // Returns the length of the disassembled machine instruction in bytes. | 327 // Returns the length of the disassembled machine instruction in bytes. |
327 int InstructionDecode(v8::internal::Vector<char> buffer, byte* instruction); | 328 int InstructionDecode(v8::internal::Vector<char> buffer, byte* instruction); |
328 | 329 |
329 private: | 330 private: |
330 enum OperandSize { | 331 enum OperandSize { |
331 BYTE_SIZE = 0, | 332 BYTE_SIZE = 0, |
332 WORD_SIZE = 1, | 333 WORD_SIZE = 1, |
333 DOUBLEWORD_SIZE = 2, | 334 DOUBLEWORD_SIZE = 2, |
334 QUADWORD_SIZE = 3 | 335 QUADWORD_SIZE = 3 |
335 }; | 336 }; |
336 | 337 |
337 const NameConverter& converter_; | 338 const NameConverter& converter_; |
338 v8::internal::EmbeddedVector<char, 128> tmp_buffer_; | 339 v8::internal::EmbeddedVector<char, 128> tmp_buffer_; |
339 unsigned int tmp_buffer_pos_; | 340 unsigned int tmp_buffer_pos_; |
340 bool abort_on_unimplemented_; | 341 bool abort_on_unimplemented_; |
341 // Prefixes parsed | 342 // Prefixes parsed |
342 byte rex_; | 343 byte rex_; |
343 byte operand_size_; // 0x66 or (if no group 3 prefix is present) 0x0. | 344 byte operand_size_; // 0x66 or (if no group 3 prefix is present) 0x0. |
344 byte group_1_prefix_; // 0xF2, 0xF3, or (if no group 1 prefix is present) 0. | 345 byte group_1_prefix_; // 0xF2, 0xF3, or (if no group 1 prefix is present) 0. |
345 // Byte size operand override. | 346 // Byte size operand override. |
346 bool byte_size_operand_; | 347 bool byte_size_operand_; |
| 348 const InstructionTable* const instruction_table_; |
347 | 349 |
348 void setRex(byte rex) { | 350 void setRex(byte rex) { |
349 ASSERT_EQ(0x40, rex & 0xF0); | 351 ASSERT_EQ(0x40, rex & 0xF0); |
350 rex_ = rex; | 352 rex_ = rex; |
351 } | 353 } |
352 | 354 |
353 bool rex() { return rex_ != 0; } | 355 bool rex() { return rex_ != 0; } |
354 | 356 |
355 bool rex_b() { return (rex_ & 0x01) != 0; } | 357 bool rex_b() { return (rex_ & 0x01) != 0; } |
356 | 358 |
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1333 setRex(current); | 1335 setRex(current); |
1334 if (rex_w()) AppendToBuffer("REX.W "); | 1336 if (rex_w()) AppendToBuffer("REX.W "); |
1335 } else if ((current & 0xFE) == 0xF2) { // Group 1 prefix (0xF2 or 0xF3). | 1337 } else if ((current & 0xFE) == 0xF2) { // Group 1 prefix (0xF2 or 0xF3). |
1336 group_1_prefix_ = current; | 1338 group_1_prefix_ = current; |
1337 } else { // Not a prefix - an opcode. | 1339 } else { // Not a prefix - an opcode. |
1338 break; | 1340 break; |
1339 } | 1341 } |
1340 data++; | 1342 data++; |
1341 } | 1343 } |
1342 | 1344 |
1343 const InstructionDesc& idesc = instruction_table.Get().Get(current); | 1345 const InstructionDesc& idesc = instruction_table_->Get(current); |
1344 byte_size_operand_ = idesc.byte_size_operation; | 1346 byte_size_operand_ = idesc.byte_size_operation; |
1345 switch (idesc.type) { | 1347 switch (idesc.type) { |
1346 case ZERO_OPERANDS_INSTR: | 1348 case ZERO_OPERANDS_INSTR: |
1347 if (current >= 0xA4 && current <= 0xA7) { | 1349 if (current >= 0xA4 && current <= 0xA7) { |
1348 // String move or compare operations. | 1350 // String move or compare operations. |
1349 if (group_1_prefix_ == REP_PREFIX) { | 1351 if (group_1_prefix_ == REP_PREFIX) { |
1350 // REP. | 1352 // REP. |
1351 AppendToBuffer("rep "); | 1353 AppendToBuffer("rep "); |
1352 } | 1354 } |
1353 if (rex_w()) AppendToBuffer("REX.W "); | 1355 if (rex_w()) AppendToBuffer("REX.W "); |
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1843 for (int i = 6 - static_cast<int>(pc - prev_pc); i >= 0; i--) { | 1845 for (int i = 6 - static_cast<int>(pc - prev_pc); i >= 0; i--) { |
1844 fprintf(f, " "); | 1846 fprintf(f, " "); |
1845 } | 1847 } |
1846 fprintf(f, " %s\n", buffer.start()); | 1848 fprintf(f, " %s\n", buffer.start()); |
1847 } | 1849 } |
1848 } | 1850 } |
1849 | 1851 |
1850 } // namespace disasm | 1852 } // namespace disasm |
1851 | 1853 |
1852 #endif // V8_TARGET_ARCH_X64 | 1854 #endif // V8_TARGET_ARCH_X64 |
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