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Unified Diff: src/trusted/validator_ragel/unreviewed/gen-dfa.cc

Issue 9968039: Add ragel machine generators to SCONS (Closed) Base URL: svn://svn.chromium.org/native_client/trunk/src/native_client/
Patch Set: Created 8 years, 8 months ago
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Index: src/trusted/validator_ragel/unreviewed/gen-dfa.cc
===================================================================
--- src/trusted/validator_ragel/unreviewed/gen-dfa.cc (revision 8170)
+++ src/trusted/validator_ragel/unreviewed/gen-dfa.cc (working copy)
@@ -12,12 +12,27 @@
#include <string.h>
#include <algorithm>
+#include <iterator>
#include <map>
#include <set>
#include <string>
#include <tuple>
#include <vector>
+#ifdef __GNUC__
+/* We use operand number formats here. They are defined in SUSv2 and supported
+ on all POSIX systems (including all versions of Linux and MacOS), yet
+ -pedantic warns about them. */
+#pragma GCC diagnostic ignored "-Wformat"
+/* GCC complains even when we explicitly use empty initializer list. Can be
+ easily fixed with data member initializers, but this requires GCC 4.7+. */
+#pragma GCC diagnostic ignored "-Wmissing-field-initializers"
+/* Default is perfectly valid way to handle missing cases. Especially if we
+ only care about very few non-default ones as often here. */
+#pragma GCC diagnostic ignored "-Wswitch-enum"
+#pragma GCC diagnostic error "-Wswitch"
+#endif
+
template <typename T, size_t N>
char (&ArraySizeHelper(T (&array)[N]))[N];
#define arraysize(array) (sizeof(ArraySizeHelper(array)))
@@ -189,7 +204,7 @@
class Instruction {
public:
- static bool check_flag_valid(const std::string &flag) {
+ static void check_flag_valid(const std::string &flag) {
if (all_instruction_flags.find(flag) == all_instruction_flags.end()) {
fprintf(stderr, "%s: unknown flag: '%s'\n",
short_program_name, flag.c_str());
@@ -568,7 +583,7 @@
fprintf(out_file, " action rel8_operand {\n"
" operand0 = JMP_TO;\n"
" base = REG_RIP;\n"
-" index = REG_NONE;\n"
+" index = NO_REG;\n"
" scale = 0;\n"
" disp_type = DISP8;\n"
" disp = p;\n"
@@ -576,7 +591,7 @@
" action rel16_operand {\n"
" operand0 = JMP_TO;\n"
" base = REG_RIP;\n"
-" index = REG_NONE;\n"
+" index = NO_REG;\n"
" scale = 0;\n"
" disp_type = DISP16;\n"
" disp = p - 1;\n"
@@ -584,7 +599,7 @@
" action rel32_operand {\n"
" operand0 = JMP_TO;\n"
" base = REG_RIP;\n"
-" index = REG_NONE;\n"
+" index = NO_REG;\n"
" scale = 0;\n"
" disp_type = DISP32;\n"
" disp = p - 3;\n"
@@ -685,23 +700,23 @@
if (ia32_mode) {
fprintf(out_file, " action modrm_only_base {\n"
" disp_type = DISPNONE;\n"
-" index = REG_NONE;\n"
+" index = NO_REG;\n"
" base = (*p) & 0x07;\n"
" scale = 0;\n"
" }\n"
" action modrm_base_disp {\n"
-" index = REG_NONE;\n"
+" index = NO_REG;\n"
" base = (*p) & 0x07;\n"
" scale = 0;\n"
" }\n"
" action modrm_pure_disp {\n"
-" base = REG_NONE;\n"
-" index = REG_NONE;\n"
+" base = NO_REG;\n"
+" index = NO_REG;\n"
" scale = 0;\n"
" }\n"
" action modrm_pure_index {\n"
" disp_type = DISPNONE;\n"
-" base = REG_NONE;\n"
+" base = NO_REG;\n"
" index = index_registers[((*p) & 0x38) >> 3];\n"
" scale = ((*p) & 0xc0) >> 6;\n"
" }\n"
@@ -714,27 +729,27 @@
} else {
fprintf(out_file, " action modrm_only_base {\n"
" disp_type = DISPNONE;\n"
-" index = REG_NONE;\n"
+" index = NO_REG;\n"
" base = ((*p) & 0x07) |\n"
" ((rex_prefix & 0x01) << 3) |\n"
" (((~vex_prefix2) & 0x20) >> 2);\n"
" scale = 0;\n"
" }\n"
" action modrm_base_disp {\n"
-" index = REG_NONE;\n"
+" index = NO_REG;\n"
" base = ((*p) & 0x07) |\n"
" ((rex_prefix & 0x01) << 3) |\n"
" (((~vex_prefix2) & 0x20) >> 2);\n"
" scale = 0;\n"
" }\n"
" action modrm_rip {\n"
-" index = REG_NONE;\n"
+" index = NO_REG;\n"
" base = REG_RIP;\n"
" scale = 0;\n"
" }\n"
" action modrm_pure_index {\n"
" disp_type = DISPNONE;\n"
-" base = REG_NONE;\n"
+" base = NO_REG;\n"
" index = index_registers[(((*p) & 0x38) >> 3) |\n"
" ((rex_prefix & 0x02) << 2) |\n"
" (((~vex_prefix2) & 0x40) >> 3)];\n"
@@ -987,7 +1002,7 @@
T { "XB", 0x80 },
T { "RXB", 0x00 }
};
- for (int vex_it = 0; vex_it < arraysize(vex_fields); ++vex_it) {
+ for (size_t vex_it = 0; vex_it < arraysize(vex_fields); ++vex_it) {
auto vex = vex_fields[vex_it];
fprintf(out_file, " VEX_%2$s = %3$s%1$s;\n"
"", enabled(Actions::kVexPrefix) && !ia32_mode ? " @vex_prefix2" : "",
@@ -1007,7 +1022,7 @@
T { "01001", 9 },
T { "01010", 10 },
};
- for (int vex_it = 0; vex_it < arraysize(vex_map); ++vex_it) {
+ for (size_t vex_it = 0; vex_it < arraysize(vex_map); ++vex_it) {
auto vex = vex_map[vex_it];
fprintf(out_file, " VEX_map%1$s = %2$s;\n"
"", vex.first, chartest((c & 0x1f) == vex.second));
@@ -1062,7 +1077,7 @@
T { "dreg", "DebugRegister" },
T { "selector", "Selector" }
};
- for (int size_it = 0; size_it < arraysize(sizes); ++size_it) {
+ for (size_t size_it = 0; size_it < arraysize(sizes); ++size_it) {
auto size = sizes[size_it];
fprintf(out_file, " action operand%1$d_%2$s {\n"
" operand%1$d_type = Operand%3$s;\n"
@@ -1072,8 +1087,8 @@
if (ia32_mode) {
fprintf(out_file, " action operand%1$d_absolute_disp {\n"
" operand%1$d = REG_RM;\n"
-" base = REG_NONE;\n"
-" index = REG_NONE;\n"
+" base = NO_REG;\n"
+" index = NO_REG;\n"
" scale = 0;\n"
" }\n"
" action operand%1$d_from_opcode {\n"
@@ -1098,7 +1113,7 @@
} else {
fprintf(out_file, " action operand%1$d_absolute_disp {\n"
" operand%1$d = REG_RM;\n"
-" base = REG_NONE;\n"
+" base = NO_REG;\n"
" index = REG_RIZ;\n"
" scale = 0;\n"
" }\n"
@@ -1141,7 +1156,7 @@
T { "rm", "REG_RM" },
T { "st", "REG_ST" }
};
- for (int type_it = 0; type_it < arraysize(types); ++type_it) {
+ for (size_t type_it = 0; type_it < arraysize(types); ++type_it) {
auto type = types[type_it];
fprintf(out_file, " action operand%1$d_%2$s {\n"
" operand%1$d = %3$s;\n"
@@ -1153,20 +1168,20 @@
if (enabled(Actions::kParseOperandsStates)) {
for (auto i = 0 ; i < 5; ++i) {
fprintf(out_file, " action operand%1$d_unused {\n"
-" operand%1$d_read = false;\n"
-" operand%1$d_write = false;\n"
+" operand%1$d_read = FALSE;\n"
+" operand%1$d_write = FALSE;\n"
" }\n"
" action operand%1$d_read {\n"
-" operand%1$d_read = true;\n"
-" operand%1$d_write = false;\n"
+" operand%1$d_read = TRUE;\n"
+" operand%1$d_write = FALSE;\n"
" }\n"
" action operand%1$d_write {\n"
-" operand%1$d_read = false;\n"
-" operand%1$d_write = true;\n"
+" operand%1$d_read = FALSE;\n"
+" operand%1$d_write = TRUE;\n"
" }\n"
" action operand%1$d_readwrite {\n"
-" operand%1$d_read = true;\n"
-" operand%1$d_write = true;\n"
+" operand%1$d_read = TRUE;\n"
+" operand%1$d_write = TRUE;\n"
" }\n"
"", i);
}
@@ -1189,7 +1204,7 @@
explicit MarkedInstruction(Instruction instruction_) :
Instruction(instruction_),
instruction_class(get_instruction_class(instruction_)),
- opcode_in_modrm(false), opcode_in_imm(false), rex { } {
+ rex { }, opcode_in_modrm(false), opcode_in_imm(false) {
if (has_flag("branch_hint")) {
optional_prefixes.insert("branch_hint");
}
@@ -1237,7 +1252,7 @@
(*opcode) = "(";
opcode->append(saved_opcode);
static const char cc[] = {'9', 'a', 'b', 'c', 'd', 'e', 'f'};
- for (int c_it = 0; c_it < arraysize(cc); ++c_it) {
+ for (size_t c_it = 0; c_it < arraysize(cc); ++c_it) {
auto c = cc[c_it];
opcode->push_back('|');
(*(saved_opcode.rbegin())) = c;
@@ -1509,7 +1524,7 @@
operand_it != operands.end(); ++operand_it) {
auto &operand = *operand_it;
static const char cc[] = {'H', 'L', 'U', 'V', 'W'};
- for (int c_it = 0; c_it < arraysize(cc); ++c_it) {
+ for (size_t c_it = 0; c_it < arraysize(cc); ++c_it) {
auto c = cc[c_it];
if ((operand.source == c) &&
(*(operand.size.rbegin()) == 'x') &&
@@ -1548,7 +1563,7 @@
}
bool modrm_memory = false;
bool modrm_register = false;
- char operand_source;
+ char operand_source = ' ';
for (auto operand_it = operands.begin();
operand_it != operands.end(); ++operand_it) {
auto &operand = *operand_it;
@@ -1672,7 +1687,7 @@
T { " operand_sib_pure_index", true, false },
T { " operand_sib_base_index", true, true }
};
- for (int mode_it = 0; mode_it < arraysize(modes); ++mode_it) {
+ for (size_t mode_it = 0; mode_it < arraysize(modes); ++mode_it) {
auto mode = modes[mode_it];
print_operator_delimeter();
if (mod_reg_is_used()) {
@@ -1752,7 +1767,7 @@
return true;
}
static const char cc[] = { 'G', 'P', 'V' };
- for (int c_it = 0; c_it < arraysize(cc); ++c_it) {
+ for (size_t c_it = 0; c_it < arraysize(cc); ++c_it) {
auto c = cc[c_it];
if (operand.source == c) {
return true;
@@ -1767,7 +1782,7 @@
operand_it != operands.end(); ++operand_it) {
auto &operand = *operand_it;
static const char cc[] = { 'E', 'M', 'N', 'Q', 'R', 'U', 'W' };
- for (int c_it = 0; c_it < arraysize(cc); ++c_it) {
+ for (size_t c_it = 0; c_it < arraysize(cc); ++c_it) {
auto c = cc[c_it];
if (operand.source == c) {
return true;
@@ -1918,12 +1933,13 @@
fprintf(out_file, " & VEX_map%s) ", opcodes[1].c_str() + 4);
auto third_byte = opcodes[2];
static const char* symbolic_names[] = { "cntl", "dest", "src1", "src" };
- for (int symbolic_it = 0;
+ for (size_t symbolic_it = 0;
symbolic_it < arraysize(symbolic_names); ++symbolic_it) {
auto symbolic = symbolic_names[symbolic_it];
for (auto it = third_byte.begin(); it != third_byte.end(); ++it) {
- if ((third_byte.end() - it) >= strlen(symbolic) &&
- !strncmp(&*it, symbolic, strlen(symbolic))) {
+ if (static_cast<size_t>(third_byte.end() - it) >=
+ strlen(symbolic) &&
+ !strncmp(&*it, symbolic, strlen(symbolic))) {
pasko-google - do not use 2012/04/05 14:16:38 I do not like how this is formatted. Should be shi
khim 2012/04/05 16:38:43 Whatever. I don't really care about this file (I h
third_byte.replace(it, it + strlen(symbolic), "XXXX");
break;
}
@@ -1945,7 +1961,8 @@
auto third_byte_ok = (arraysize(third_byte_check) ==
third_byte.length());
pasko-google - do not use 2012/04/05 14:16:38 spacing, better be: bool third_byte_ok = (arra
khim 2012/04/05 16:38:43 Done.
if (third_byte_ok) {
- for (int set_it = 0; set_it < arraysize(third_byte_check); ++set_it) {
+ for (size_t set_it = 0; set_it < arraysize(third_byte_check);
+ ++set_it) {
pasko-google - do not use 2012/04/05 14:16:38 shiftwidth = 4
khim 2012/04/05 16:38:43 Done.
auto &set = third_byte_check[set_it];
if (set.find(third_byte[&set - third_byte_check]) == set.end()) {
third_byte_ok = false;

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