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Side by Side Diff: src/trusted/validator_ragel/unreviewed/decoder.h

Issue 9968039: Add ragel machine generators to SCONS (Closed) Base URL: svn://svn.chromium.org/native_client/trunk/src/native_client/
Patch Set: Created 8 years, 8 months ago
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1 /* 1 /*
2 * Copyright (c) 2011 The Native Client Authors. All rights reserved. 2 * Copyright (c) 2011 The Native Client Authors. All rights reserved.
3 * Use of this source code is governed by a BSD-style license that can be 3 * Use of this source code is governed by a BSD-style license that can be
4 * found in the LICENSE file. 4 * found in the LICENSE file.
5 */ 5 */
6 6
7 #ifndef _DECODER_X86_64_H_ 7 #ifndef _DECODER_X86_64_H_
8 #define _DECODER_X86_64_H_ 8 #define _DECODER_X86_64_H_
9 9
10 #include <inttypes.h> 10 #if NACL_WINDOWS
11 #include <windows.h>
12 #include "native_client/src/include/portability.h"
13
14 /*
15 * Microsoft C/C++ version 14.00.50727.762, which comes with Visual C++ 2005,
16 * and version 15.00.30729.01, which comes with Visual C++ 2008, do not.
17 * define _Bool.
18 */
19 #if defined(_MSC_VER) && _MSC_VER <= 1500
20 typedef int _Bool;
21 #endif
22 #else
23 #include <stdint.h>
24 #include <stdbool.h>
25 #endif
11 26
12 #ifdef __cplusplus 27 #ifdef __cplusplus
13 extern "C" { 28 extern "C" {
14 #endif 29 #endif
15 30
16 enum operand_type { 31 enum operand_type {
17 OperandSize2bit, /* See VPERMIL2Px instruction for description. */ 32 OperandSize2bit, /* See VPERMIL2Px instruction for description. */
18 OperandSize8bit, 33 OperandSize8bit,
19 OperandSize16bit, 34 OperandSize16bit,
20 OperandSize32bit, 35 OperandSize32bit,
(...skipping 41 matching lines...) Expand 10 before | Expand all | Expand 10 after
62 REG_R15, 77 REG_R15,
63 REG_RM, /* Address in memory via rm field. */ 78 REG_RM, /* Address in memory via rm field. */
64 REG_RIP, /* RIP - used as base in x86-64 mode. */ 79 REG_RIP, /* RIP - used as base in x86-64 mode. */
65 REG_RIZ, /* EIZ/RIZ - used as "always zero index" register. */ 80 REG_RIZ, /* EIZ/RIZ - used as "always zero index" register. */
66 REG_IMM, /* Fixed value in imm field. */ 81 REG_IMM, /* Fixed value in imm field. */
67 REG_IMM2, /* Fixed value in second imm field. */ 82 REG_IMM2, /* Fixed value in second imm field. */
68 REG_DS_RBX, /* Fox xlat: %ds(%rbx). */ 83 REG_DS_RBX, /* Fox xlat: %ds(%rbx). */
69 REG_ES_RDI, /* For string instructions: %es:(%rsi). */ 84 REG_ES_RDI, /* For string instructions: %es:(%rsi). */
70 REG_DS_RSI, /* For string instructions: %ds:(%rdi). */ 85 REG_DS_RSI, /* For string instructions: %ds:(%rdi). */
71 REG_PORT_DX, /* 16-bit DX: for in/out instructions. */ 86 REG_PORT_DX, /* 16-bit DX: for in/out instructions. */
72 REG_NONE, /* For modrm: both index and base can be absent. */ 87 NO_REG, /* For modrm: both index and base can be absent. */
73 REG_ST, /* For x87 instructions: implicit %st. */ 88 REG_ST, /* For x87 instructions: implicit %st. */
74 JMP_TO /* Operand is jump target address: usually %rip+offset. */ 89 JMP_TO /* Operand is jump target address: usually %rip+offset. */
75 }; 90 };
76 91
77 struct instruction { 92 struct instruction {
78 const char *name; 93 const char *name;
79 unsigned char operands_count; 94 unsigned char operands_count;
80 struct { 95 struct {
81 unsigned char rex; /* Mostly to distingush cases like %ah vs %spl. */ 96 unsigned char rex; /* Mostly to distingush cases like %ah vs %spl. */
82 _Bool data16:1; /* "Normal", non-rex prefixes. */ 97 _Bool data16:1; /* "Normal", non-rex prefixes. */
(...skipping 29 matching lines...) Expand all
112 127
113 int DecodeChunkIA32(const uint8_t *data, size_t size, 128 int DecodeChunkIA32(const uint8_t *data, size_t size,
114 process_instruction_func process_instruction, 129 process_instruction_func process_instruction,
115 process_error_func process_error, void *userdata); 130 process_error_func process_error, void *userdata);
116 131
117 #ifdef __cplusplus 132 #ifdef __cplusplus
118 } 133 }
119 #endif 134 #endif
120 135
121 #endif 136 #endif
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