Add ragel machine generators to SCONS

src/trusted/validator_ragel/unreviewed/decoder-test.c

 /*
  * Copyright (c) 2012 The Native Client Authors. All rights reserved.
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 #include <assert.h>
-#include <elf.h>
-#include <inttypes.h>
 #include <stdio.h>
 #include <stdlib.h>
 #include <string.h>
-#include "decoder.h"
+
+#include "native_client/src/include/elf32.h"
+#include "native_client/src/include/elf64.h"
+#include "native_client/src/trusted/validator_ragel/unreviewed/decoder.h"
 
 #undef TRUE
 #define TRUE    1
 
 #undef FALSE
 #define FALSE   0
 
 static void CheckBounds(unsigned char *data, size_t data_size,
                         void *ptr, size_t inside_size) {
   assert(data <= (unsigned char *) ptr);
@@ skipping 499 matching lines @@
                 instruction->operands[i].name -= 8;
                 --rex_bits;
               }
             }
           }
         }
       } else if (instruction->operands[i].name == REG_RM) {
         if ((instruction->rm.base >= REG_R8) &&
             (instruction->rm.base <= REG_R15)) {
           ++rex_bits;
-        } else if ((instruction->rm.base == REG_NONE) ||
+        } else if ((instruction->rm.base == NO_REG) ||
                    (instruction->rm.base == REG_RIP)) {
           ++maybe_rex_bits;
         }
         if ((instruction->rm.index >= REG_R8) &&
             (instruction->rm.index <= REG_R15)) {
           ++rex_bits;
         }
       }
     }
   }
@@ skipping 601 matching lines @@
       break;
       case REG_ST:
         assert(operand_type == OperandST);
         printf("%%st");
         break;
       case REG_RM: {
         if (instruction->rm.offset) {
           printf("0x%"PRIx64, instruction->rm.offset);
         }
         if (((struct DecodeState *)userdata)->ia32_mode) {
-          if ((instruction->rm.base != REG_NONE) ||
-              (instruction->rm.index != REG_NONE) ||
+          if ((instruction->rm.base != NO_REG) ||
+              (instruction->rm.index != NO_REG) ||
               (instruction->rm.scale != 0)) {
             printf("(");
           }
           switch (instruction->rm.base) {
             case REG_RAX: printf("%%eax"); break;
             case REG_RCX: printf("%%ecx"); break;
             case REG_RDX: printf("%%edx"); break;
             case REG_RBX: printf("%%ebx"); break;
             case REG_RSP: printf("%%esp"); break;
             case REG_RBP: printf("%%ebp"); break;
             case REG_RSI: printf("%%esi"); break;
             case REG_RDI: printf("%%edi"); break;
-            case REG_NONE: break;
+            case NO_REG: break;
             case REG_R8:
             case REG_R9:
             case REG_R10:
             case REG_R11:
             case REG_R12:
             case REG_R13:
             case REG_R14:
             case REG_R15:
             case REG_RIP:
             case REG_RM:
@@ skipping 14 matching lines @@
             case REG_RDX: printf(",%%edx,%d",1<<instruction->rm.scale); break;
             case REG_RBX: printf(",%%ebx,%d",1<<instruction->rm.scale); break;
             case REG_RSP: printf(",%%esp,%d",1<<instruction->rm.scale); break;
             case REG_RBP: printf(",%%ebp,%d",1<<instruction->rm.scale); break;
             case REG_RSI: printf(",%%esi,%d",1<<instruction->rm.scale); break;
             case REG_RDI: printf(",%%edi,%d",1<<instruction->rm.scale); break;
             case REG_RIZ: if ((instruction->rm.base != REG_RSP) ||
                               (instruction->rm.scale != 0))
                 printf(",%%eiz,%d",1<<instruction->rm.scale);
               break;
-            case REG_NONE: break;
+            case NO_REG: break;
             case REG_R8:
             case REG_R9:
             case REG_R10:
             case REG_R11:
             case REG_R12:
             case REG_R13:
             case REG_R14:
             case REG_R15:
             case REG_RM:
             case REG_RIP:
             case REG_IMM:
             case REG_IMM2:
             case REG_DS_RBX:
             case REG_ES_RDI:
             case REG_DS_RSI:
             case REG_PORT_DX:
             case REG_ST:
             case JMP_TO:
               assert(FALSE);
           }
-          if ((instruction->rm.base != REG_NONE) ||
-              (instruction->rm.index != REG_NONE) ||
+          if ((instruction->rm.base != NO_REG) ||
+              (instruction->rm.index != NO_REG) ||
               (instruction->rm.scale != 0)) {
             printf(")");
           }
         } else {
-          if ((instruction->rm.base != REG_NONE) ||
+          if ((instruction->rm.base != NO_REG) ||
               (instruction->rm.index != REG_RIZ) ||
               (instruction->rm.scale != 0)) {
             printf("(");
           }
           switch (instruction->rm.base) {
             case REG_RAX: printf("%%rax"); break;
             case REG_RCX: printf("%%rcx"); break;
             case REG_RDX: printf("%%rdx"); break;
             case REG_RBX: printf("%%rbx"); break;
             case REG_RSP: printf("%%rsp"); break;
             case REG_RBP: printf("%%rbp"); break;
             case REG_RSI: printf("%%rsi"); break;
             case REG_RDI: printf("%%rdi"); break;
             case REG_R8: printf("%%r8"); break;
             case REG_R9: printf("%%r9"); break;
             case REG_R10: printf("%%r10"); break;
             case REG_R11: printf("%%r11"); break;
             case REG_R12: printf("%%r12"); break;
             case REG_R13: printf("%%r13"); break;
             case REG_R14: printf("%%r14"); break;
             case REG_R15: printf("%%r15"); break;
             case REG_RIP: printf("%%rip"); print_rip = TRUE; break;
-            case REG_NONE: break;
+            case NO_REG: break;
             case REG_RM:
             case REG_RIZ:
             case REG_IMM:
             case REG_IMM2:
             case REG_DS_RBX:
             case REG_ES_RDI:
             case REG_DS_RSI:
             case REG_PORT_DX:
             case REG_ST:
             case JMP_TO:
               assert(FALSE);
           }
           switch (instruction->rm.index) {
             case REG_RAX: printf(",%%rax,%d",1<<instruction->rm.scale); break;
             case REG_RCX: printf(",%%rcx,%d",1<<instruction->rm.scale); break;
             case REG_RDX: printf(",%%rdx,%d",1<<instruction->rm.scale); break;
             case REG_RBX: printf(",%%rbx,%d",1<<instruction->rm.scale); break;
             case REG_RSP: printf(",%%rsp,%d",1<<instruction->rm.scale); break;
             case REG_RBP: printf(",%%rbp,%d",1<<instruction->rm.scale); break;
             case REG_RSI: printf(",%%rsi,%d",1<<instruction->rm.scale); break;
             case REG_RDI: printf(",%%rdi,%d",1<<instruction->rm.scale); break;
             case REG_R8: printf(",%%r8,%d",1<<instruction->rm.scale); break;
             case REG_R9: printf(",%%r9,%d",1<<instruction->rm.scale); break;
             case REG_R10: printf(",%%r10,%d",1<<instruction->rm.scale); break;
             case REG_R11: printf(",%%r11,%d",1<<instruction->rm.scale); break;
             case REG_R12: printf(",%%r12,%d",1<<instruction->rm.scale); break;
             case REG_R13: printf(",%%r13,%d",1<<instruction->rm.scale); break;
             case REG_R14: printf(",%%r14,%d",1<<instruction->rm.scale); break;
             case REG_R15: printf(",%%r15,%d",1<<instruction->rm.scale); break;
-            case REG_RIZ: if (((instruction->rm.base != REG_NONE) &&
+            case REG_RIZ: if (((instruction->rm.base != NO_REG) &&
                                (instruction->rm.base != REG_RSP) &&
                                (instruction->rm.base != REG_R12)) ||
                                (instruction->rm.scale != 0))
                 printf(",%%riz,%d",1<<instruction->rm.scale);
               break;
-            case REG_NONE: break;
+            case NO_REG: break;
             case REG_RM:
             case REG_RIP:
             case REG_IMM:
             case REG_IMM2:
             case REG_DS_RBX:
             case REG_ES_RDI:
             case REG_DS_RSI:
             case REG_PORT_DX:
             case REG_ST:
             case JMP_TO:
               assert(FALSE);
           }
-          if ((instruction->rm.base != REG_NONE) ||
+          if ((instruction->rm.base != NO_REG) ||
               (instruction->rm.index != REG_RIZ) ||
               (instruction->rm.scale != 0)) {
             printf(")");
           }
         }
       }
       break;
       case REG_IMM: {
         printf("$0x%"PRIx64,instruction->imm[0]);
         break;
@@ skipping 23 matching lines @@
         break;
       case JMP_TO: if (instruction->operands[0].type == OperandSize16bit)
           printf("0x%zx", ((end + instruction->rm.offset -
                          (((struct DecodeState *)userdata)->offset)) & 0xffff));
         else
           printf("0x%zx", (end + instruction->rm.offset -
                                    (((struct DecodeState *)userdata)->offset)));
         break;
       case REG_RIP:
       case REG_RIZ:
-      case REG_NONE:
+      case NO_REG:
         assert(FALSE);
     }
     delimeter = ',';
   }
   if (print_rip) {
     printf("        # 0x%8"PRIx64,
            (uint64_t) (end + instruction->rm.offset -
                (((struct DecodeState *)userdata)->offset)));
   }
   printf("\n");
@@ skipping 136 matching lines @@
   for (index = initial_index; index < argc; ++index) {
     const char *filename = argv[index];
     int rc = DecodeFile(filename, repeat_count);
     if (rc != 0) {
       printf("file '%s' can not be fully decoded\n", filename);
       return 1;
     }
   }
   return 0;
 }