| Index: src/trusted/validator_arm/gen/arm32_decode.h
|
| ===================================================================
|
| --- src/trusted/validator_arm/gen/arm32_decode.h (revision 8201)
|
| +++ src/trusted/validator_arm/gen/arm32_decode.h (working copy)
|
| @@ -18,62 +18,128 @@
|
| /*
|
| * Defines a stateless decoder class selector for instructions
|
| */
|
| -/*
|
| - * Define the class decoders used by this decoder state.
|
| - */
|
| -class Arm32DecoderState : DecoderState {
|
| +class Arm32DecoderState : nacl_arm_dec::DecoderState {
|
| public:
|
| - // Generates an instance of a decoder state.
|
| + /*
|
| + * Generates an instance of a decoder state.
|
| + */
|
| explicit Arm32DecoderState();
|
| virtual ~Arm32DecoderState();
|
|
|
| - // Parses the given instruction, returning the decoder to use.
|
| - virtual const class ClassDecoder &decode(const Instruction) const;
|
| + /*
|
| + * Parses the given instruction, returning the decoder to use.
|
| + */
|
| + virtual const class nacl_arm_dec::ClassDecoder
|
| + &decode(const nacl_arm_dec::Instruction) const;
|
|
|
| - // Define the decoders to use in this decoder state
|
| - CoprocessorOp CoprocessorOp_instance_;
|
| - ImmediateBic ImmediateBic_instance_;
|
| - LoadMultiple LoadMultiple_instance_;
|
| - LoadCoprocessor LoadCoprocessor_instance_;
|
| - LoadDoubleExclusive LoadDoubleExclusive_instance_;
|
| - Branch Branch_instance_;
|
| - Test Test_instance_;
|
| - StoreRegister StoreRegister_instance_;
|
| - MoveDoubleFromCoprocessor MoveDoubleFromCoprocessor_instance_;
|
| - TestImmediate TestImmediate_instance_;
|
| - BxBlx BxBlx_instance_;
|
| - EffectiveNoOp EffectiveNoOp_instance_;
|
| - LongMultiply LongMultiply_instance_;
|
| - Binary4RegisterShiftedOp Binary4RegisterShiftedOp_instance_;
|
| - Breakpoint Breakpoint_instance_;
|
| - Multiply Multiply_instance_;
|
| - PackSatRev PackSatRev_instance_;
|
| - LoadExclusive LoadExclusive_instance_;
|
| - VectorStore VectorStore_instance_;
|
| - Unary3RegisterShiftedOp Unary3RegisterShiftedOp_instance_;
|
| - Undefined Undefined_instance_;
|
| - DataProc DataProc_instance_;
|
| - Deprecated Deprecated_instance_;
|
| - LoadImmediate LoadImmediate_instance_;
|
| - StoreCoprocessor StoreCoprocessor_instance_;
|
| - Roadblock Roadblock_instance_;
|
| - LoadDoubleR LoadDoubleR_instance_;
|
| - StoreExclusive StoreExclusive_instance_;
|
| - StoreImmediate StoreImmediate_instance_;
|
| - MoveFromCoprocessor MoveFromCoprocessor_instance_;
|
| - LoadRegister LoadRegister_instance_;
|
| - LoadDoubleI LoadDoubleI_instance_;
|
| - Binary3RegisterShiftedTest Binary3RegisterShiftedTest_instance_;
|
| - Unpredictable Unpredictable_instance_;
|
| - Forbidden Forbidden_instance_;
|
| - VectorLoad VectorLoad_instance_;
|
| - MoveToStatusRegister MoveToStatusRegister_instance_;
|
| - SatAddSub SatAddSub_instance_;
|
| + private:
|
| + /*
|
| + * Define the class decoders used by this decoder state.
|
| + */
|
| + const CoprocessorOp CoprocessorOp_instance_;
|
| + const MoveToStatusRegister MoveToStatusRegister_instance_;
|
| + const ImmediateBic ImmediateBic_instance_;
|
| + const LoadMultiple LoadMultiple_instance_;
|
| + const LoadCoprocessor LoadCoprocessor_instance_;
|
| + const LongMultiply LongMultiply_instance_;
|
| + const Branch Branch_instance_;
|
| + const Test Test_instance_;
|
| + const StoreRegister StoreRegister_instance_;
|
| + const LoadRegister LoadRegister_instance_;
|
| + const TestImmediate TestImmediate_instance_;
|
| + const VectorLoad VectorLoad_instance_;
|
| + const EffectiveNoOp EffectiveNoOp_instance_;
|
| + const LoadDoubleExclusive LoadDoubleExclusive_instance_;
|
| + const Binary4RegisterShiftedOp Binary4RegisterShiftedOp_instance_;
|
| + const Breakpoint Breakpoint_instance_;
|
| + const Multiply Multiply_instance_;
|
| + const PackSatRev PackSatRev_instance_;
|
| + const LoadExclusive LoadExclusive_instance_;
|
| + const VectorStore VectorStore_instance_;
|
| + const Unary3RegisterShiftedOp Unary3RegisterShiftedOp_instance_;
|
| + const Undefined Undefined_instance_;
|
| + const DataProc DataProc_instance_;
|
| + const Deprecated Deprecated_instance_;
|
| + const LoadImmediate LoadImmediate_instance_;
|
| + const StoreCoprocessor StoreCoprocessor_instance_;
|
| + const Roadblock Roadblock_instance_;
|
| + const MoveFromCoprocessor MoveFromCoprocessor_instance_;
|
| + const StoreExclusive StoreExclusive_instance_;
|
| + const StoreImmediate StoreImmediate_instance_;
|
| + const MoveDoubleFromCoprocessor MoveDoubleFromCoprocessor_instance_;
|
| + const SatAddSub SatAddSub_instance_;
|
| + const LoadDoubleI LoadDoubleI_instance_;
|
| + const Binary3RegisterShiftedTest Binary3RegisterShiftedTest_instance_;
|
| + const Unpredictable Unpredictable_instance_;
|
| + const Forbidden Forbidden_instance_;
|
| + const BxBlx BxBlx_instance_;
|
| + const LoadDoubleR LoadDoubleR_instance_;
|
|
|
| - private:
|
| - // Don't allow the following!
|
| - explicit Arm32DecoderState(const Arm32DecoderState&);
|
| - void operator=(const Arm32DecoderState&);
|
| + /*
|
| + * Prototypes for static table-matching functions.
|
| + */
|
| + inline const ClassDecoder &decode_ARMv7( const nacl_arm_dec::Instruction insn) const;
|
| +
|
| + inline const ClassDecoder &decode_dp_misc( const nacl_arm_dec::Instruction insn) const;
|
| +
|
| + inline const ClassDecoder &decode_dp_reg( const nacl_arm_dec::Instruction insn) const;
|
| +
|
| + inline const ClassDecoder &decode_dp_reg_shifted( const nacl_arm_dec::Instruction insn) const;
|
| +
|
| + inline const ClassDecoder &decode_dp_immed( const nacl_arm_dec::Instruction insn) const;
|
| +
|
| + inline const ClassDecoder &decode_mult( const nacl_arm_dec::Instruction insn) const;
|
| +
|
| + inline const ClassDecoder &decode_sat_add_sub( const nacl_arm_dec::Instruction insn) const;
|
| +
|
| + inline const ClassDecoder &decode_half_mult( const nacl_arm_dec::Instruction insn) const;
|
| +
|
| + inline const ClassDecoder &decode_extra_load_store( const nacl_arm_dec::Instruction insn) const;
|
| +
|
| + inline const ClassDecoder &decode_sync( const nacl_arm_dec::Instruction insn) const;
|
| +
|
| + inline const ClassDecoder &decode_msr_and_hints( const nacl_arm_dec::Instruction insn) const;
|
| +
|
| + inline const ClassDecoder &decode_misc( const nacl_arm_dec::Instruction insn) const;
|
| +
|
| + inline const ClassDecoder &decode_load_store_word_byte( const nacl_arm_dec::Instruction insn) const;
|
| +
|
| + inline const ClassDecoder &decode_media( const nacl_arm_dec::Instruction insn) const;
|
| +
|
| + inline const ClassDecoder &decode_parallel_add_sub( const nacl_arm_dec::Instruction insn) const;
|
| +
|
| + inline const ClassDecoder &decode_pack_sat_rev( const nacl_arm_dec::Instruction insn) const;
|
| +
|
| + inline const ClassDecoder &decode_signed_mult( const nacl_arm_dec::Instruction insn) const;
|
| +
|
| + inline const ClassDecoder &decode_branch_block_xfer( const nacl_arm_dec::Instruction insn) const;
|
| +
|
| + inline const ClassDecoder &decode_super_cop( const nacl_arm_dec::Instruction insn) const;
|
| +
|
| + inline const ClassDecoder &decode_unconditional( const nacl_arm_dec::Instruction insn) const;
|
| +
|
| + inline const ClassDecoder &decode_misc_hints_simd( const nacl_arm_dec::Instruction insn) const;
|
| +
|
| + inline const ClassDecoder &decode_simd_dp( const nacl_arm_dec::Instruction insn) const;
|
| +
|
| + inline const ClassDecoder &decode_simd_dp_3same( const nacl_arm_dec::Instruction insn) const;
|
| +
|
| + inline const ClassDecoder &decode_simd_dp_3diff( const nacl_arm_dec::Instruction insn) const;
|
| +
|
| + inline const ClassDecoder &decode_simd_dp_2scalar( const nacl_arm_dec::Instruction insn) const;
|
| +
|
| + inline const ClassDecoder &decode_simd_dp_2shift( const nacl_arm_dec::Instruction insn) const;
|
| +
|
| + inline const ClassDecoder &decode_simd_dp_2misc( const nacl_arm_dec::Instruction insn) const;
|
| +
|
| + inline const ClassDecoder &decode_simd_dp_1imm( const nacl_arm_dec::Instruction insn) const;
|
| +
|
| + inline const ClassDecoder &decode_simd_load_store( const nacl_arm_dec::Instruction insn) const;
|
| +
|
| + inline const ClassDecoder &decode_simd_load_store_l0( const nacl_arm_dec::Instruction insn) const;
|
| +
|
| + inline const ClassDecoder &decode_simd_load_store_l1( const nacl_arm_dec::Instruction insn) const;
|
| +
|
| };
|
|
|
| } // namespace
|
|
|