Finish separation of testing from sel_ldr validation. Also, automate

src/trusted/validator_arm/inst_classes.cc

 /*
  * Copyright (c) 2012 The Native Client Authors. All rights reserved.
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 #include "native_client/src/trusted/validator_arm/inst_classes.h"
 
 #include <assert.h>
 #include <string.h>
 
 // Implementations of instruction classes, for those not completely defined in
 // in the header.
 
 namespace nacl_arm_dec {
 
-const char* ClassDecoder::name() const {
-  // This should never be called!
-  assert(0);
-  return "???";
-}
-
 uint32_t ShiftTypeBits5To6Interface::ComputeDecodeImmShift(
     uint32_t shift_type, uint32_t imm5_value) {
   switch (shift_type) {
     case 0:
       return imm5_value;
     case 1:
     case 2:
       return imm5_value == 0 ? 32 : imm5_value;
     case 3:
       return imm5_value == 0 ? 1 : imm5_value;
@@ skipping 46 matching lines @@
 
 RegisterList Unary2RegisterOp::defs(const Instruction i) const {
   return d_.reg(i) + flags_.reg_if_updated(i);
 }
 
 // Binary3RegisterOp
 SafetyLevel Binary3RegisterOp::safety(const Instruction i) const {
   // Unsafe if any register contains PC (ARM restriction).
   if ((d_.reg(i) + m_.reg(i) + n_.reg(i))[kRegisterPc]) return UNPREDICTABLE;
 
+
   // Note: We would restrict out PC as well for Rd in NaCl, but no need
   // since the ARM restriction doesn't allow it anyway.
   return MAY_BE_SAFE;
 }
 
 RegisterList Binary3RegisterOp::defs(const Instruction i) const {
   return d_.reg(i) + flags_.reg_if_updated(i);
 }
 
 // Unary2RegisterImmedShiftedOp
@@ skipping 478 matching lines @@
   return kRegisterPc + (PreindexingFlag(i) ? kRegisterLink : kRegisterNone);
 }
 
 int32_t Branch::branch_target_offset(const Instruction i) const {
   // Sign extend and shift left 2:
   int32_t offset = (int32_t)(i.bits(23, 0) << 8) >> 6;
   return offset + 8;  // because r15 reads as 8 bytes ahead
 }
 
 }  // namespace